Ross Thompson
930e00b69b
Added new submodule for digilent fpga boards.
2023-07-17 16:25:37 -05:00
Victor Clements
e3856708d0
pulling in FreeRTOS/kernel Submodule
2023-06-13 10:41:18 -07:00
Ross Thompson
fc9081b64c
Added Yujun Lin's branch predictor simulator. This is a C baseline module for common branch predictor algorithms.
2023-03-07 10:49:59 -06:00
Daniel Torres
dad913cb82
fixed gitmodules
2022-07-21 10:15:13 -07:00
Daniel Torres
e9aedfdc53
changed the default branch of embench
2022-07-21 10:14:05 -07:00
David Harris
149301db32
Removed Sky130 libraries
2022-07-06 13:50:11 +00:00
DTowersM
8178a6732b
added back the .git ignore and .git modules for the coremark directory, also added graphGen to the main repo
2022-06-13 23:33:10 +00:00
DTowersM
1f4d56ba32
added back working coremark in benchmarks/riscv64-bcoremarkdirectory, experimental simplifications are in benchmarkscoremark/ but this doesn't currently work (some type of c bug)
2022-06-13 23:23:57 +00:00
James Stine
60e19e3b67
Added the 12T submodule to the project.
2022-02-03 19:26:41 -06:00
David Harris
96a0baade4
Removed soc_flow
2022-01-31 22:58:33 +00:00
David Harris
3016b46d65
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2022-01-31 00:59:49 +00:00
David Harris
71f7d66dbf
gitmodules
2022-01-31 00:59:44 +00:00
James Stine
8fd975da74
Remove book_flow to add back later - will add synthDC back within 30m
2022-01-28 08:18:30 -06:00
David Harris
064a02de18
Added synthesis submodules
2022-01-27 14:31:34 +00:00
David Harris
55b4423329
Added E extension, and downloaded riscv-dv and embench-iot to addins
2022-01-17 14:42:59 +00:00
David Harris
486cfdc3a5
Added C test cases
2022-01-11 21:01:48 +00:00
David Harris
50b43d3d64
.gitmodule added dirty riscv-arch-test
2021-12-29 23:50:17 +00:00
David Harris
48bb534658
Started FIR test code and started incorporating Imperas tests
2021-12-25 22:39:51 +00:00
David Harris
787af4287e
Removed riscv-isa-sim submodule from Wally; use it in /opt/riscv instead
2021-12-21 02:35:41 +00:00
Kevin Kim
cae3a44b9a
added arch-test submodule
2021-11-30 18:22:08 -08:00
Kevin Kim
b5e86b2e20
Added git submodules
...
-riscv-arch-test
-rscv-isa-sim
submodules are added in addins/ directory
2021-11-30 18:16:37 -08:00
kipmacsaigoren
2cd2fe0828
Added git things to make it all a little nicer and synthesis work.
2021-09-15 12:15:53 -05:00
Teo Ene
ec21126474
Flow updated for 90nm
2021-07-01 13:32:42 -05:00
Teo Ene
72dd97d9b6
sky130 18T and 15T cell libraries removed
...
Upon noticing their size, concerns were raised about available drive space.
As 12T is the main implementation focus, the decision was made to remove 15T and 18T.
Apologies if any were interested in implementing the processor across multiple standard cell libraries for comparison.
2021-02-14 09:05:41 -06:00
Teo Ene
cc077da2bb
Removed riscv-o3 module
2021-02-12 16:08:34 -06:00
Teo Ene
4e0b13696b
Added synth and PnR flow
2021-01-25 14:28:14 -06:00
