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2,375 Commits 4 Branches 2 Tags 52 MiB
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14 Commits

Author SHA1 Message Date
David Harris
57d32e58c6 Switched riscv-arch-test to current hash 2021-12-29 18:52:52 +00:00
David Harris
c3bfa53db0 Added partially working MMU tests 2021-12-29 03:14:16 +00:00
David Harris
e97e512da9 Started FIR test code and started incorporating Imperas tests 2021-12-25 22:39:51 +00:00
David Harris
434f49c03e Removed riscv-isa-sim submodule from Wally; use it in /opt/riscv instead 2021-12-21 02:35:41 +00:00
David Harris
7a8162497b Added irscv-arch-test and rsicv-isa-sim 2021-12-15 12:38:35 -08:00
Ross Thompson
f061a26411 Cleaned up fpga synthesis script. 2021-12-13 18:26:54 -06:00
David Harris
74cf0eb96a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-13 07:57:49 -08:00
kwan
5ede8126fd priviledge .* removed, passed regression 2021-12-13 00:34:43 -08:00
David Harris
5d4014d351 Refactoring ALU and datapath muxes 2021-12-08 12:33:53 -08:00
Katherine Parry
d0e708f239 FMA uses one LOA 2021-12-07 14:15:43 -08:00
kwan
2a77bc8053 .* in ifu/ifu.sv eliminated 2021-12-02 09:45:55 -08:00
David Harris
e4861e11d1 Added coremark scripts to regression directory 2021-12-01 09:08:06 -08:00
Kevin Kim
869cd44533 added arch-test submodule 2021-11-30 18:22:08 -08:00
Kevin Kim
6323609da9 Added git submodules 
-riscv-arch-test
-rscv-isa-sim
submodules are added in addins/ directory
 2021-11-30 18:16:37 -08:00