Ross Thompson
96781e0b2a
Yay! We now have a functional ila and the uart connection on the pc side works. However the CPU is stuck in reset. Not really sure what's going on there.
2023-04-17 16:00:02 -05:00
Ross Thompson
fad0366d26
Adding in the ILA to the arty a7.
2023-04-17 14:54:10 -05:00
Ross Thompson
0be81fdfc8
Lowered arty a7 clock frequency to 15Mhz to meet timing. can probalby go faster.
2023-04-17 12:16:31 -05:00
Ross Thompson
a7a362f82e
Finally got the arty a7 to build.
2023-04-17 11:54:22 -05:00
Ross Thompson
9070b4adf5
OMG. the ddr3 has it's own mmcm (pll) which had incorreclty specified the input clock period as 3000 ps rather than 6000 ps so the pll was running at twice the speed. I speed the whole weekend on this. :(
2023-04-17 11:10:19 -05:00
Ross Thompson
5da5b76449
Fixed more issues with arty a7 constarints.
2023-04-16 13:25:02 -05:00
Ross Thompson
d2272c0620
Found and fixed the major architecture issue with the mig 7 used in the arty a7 board.
...
mig 7 is completely different from the ddr4 mig in that the internal pll does not general the required clocks. An external mmcm is required to general two inputs clocks and the required user clock.
2023-04-15 11:13:28 -05:00
Ross Thompson
c9445384d7
Realized we need a separate mmcm when using the mig 7 for ddr3 rather than the ddr4 mig. Go figure.
2023-04-14 18:02:16 -05:00
Ross Thompson
b5799c896e
Finally fixed the ddr3 mig script to work correclty.
2023-04-14 11:41:51 -05:00
Ross Thompson
679dc7d73b
Progress on arty a7 board.
2023-04-13 17:57:12 -05:00
Ross Thompson
1861ca8c86
Fixed more bugs in the ila debug constraints.
2023-04-11 14:32:53 -05:00
Ross Thompson
0a43c43b0a
Merge branch 'main' of github.com:ross144/cvw
2023-04-11 14:31:08 -05:00
Ross Thompson
b015e736a0
Updated to help debut Jacob's crossbar woes.
2023-04-11 14:22:42 -05:00
Ross Thompson
c7104bebd3
Fixed sum bugs with arty a7 ila script.
2023-04-11 10:00:06 -05:00
Ross Thompson
6123efd5b2
Updates for arty a7.
2023-04-10 17:02:19 -05:00
Ross Thompson
2abd164d03
Fixed syntax errors in arty7 top level.
2023-04-10 16:08:40 -05:00
Ross Thompson
81fb076e9e
Added more support for Arty A7 board.
2023-04-10 16:01:17 -05:00
Ross Thompson
d2d528cf3c
Finally building ddr3 xilinx ip from script.
2023-04-10 14:36:33 -05:00
Ross Thompson
5aa614858f
Started putting together the arty a7 board package files.
2023-04-10 13:15:55 -05:00
Ross Thompson
d67ee33896
Updated wally figure again to increase resolution.
2023-04-09 12:26:15 -05:00
Ross Thompson
f6c84b1e8d
Updated wally top level figure to fix issue 172.
2023-04-09 12:20:43 -05:00
Ross Thompson
132016f131
Merge branch 'main' of https://github.com/openhwgroup/cvw into main
2023-04-09 12:19:44 -05:00
David Harris
11cadb3f8f
Merge pull request #222 from kjprime/main
...
Remove unnecessary check from compressed instruction decode
2023-04-09 04:56:21 -07:00
David Harris
c8cd2ffc77
Merge pull request #221 from dherreravicioso/main
...
Added test coverage for Privilege Unit in CSRs
2023-04-09 04:54:36 -07:00
Kevin Thomas
640310cf94
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-04-08 22:56:20 -05:00
Diego Herrera Vicioso
76d5c3e500
Added test coverage for floating point registers, some PMP addresses, as well as MTVAL and MCAUSE CSRs.
2023-04-08 16:40:36 -07:00
Ross Thompson
e79119e2fd
Merge pull request #220 from davidharrishmc/dev
...
Obscure coverage fixes
2023-04-08 10:27:31 -05:00
David Harris
d27779f4c0
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-04-07 21:57:18 -07:00
David Harris
4a2f641348
Waived coverage on BTB memory with byte write enables tied high
2023-04-07 21:56:49 -07:00
David Harris
495f2ed274
Improved RAS predictor coverage by eliminating unreachable StallM term
2023-04-07 21:37:12 -07:00
Ross Thompson
a36a8ef6f5
Merge pull request #219 from davidharrishmc/dev
...
Spill logic coverage and fdivsqrt cleanup
2023-04-07 23:30:52 -05:00
David Harris
5119222c2f
Commented WFI non-flush in writeback stage of hazard unit
2023-04-07 21:27:13 -07:00
David Harris
a9b7bd101e
Added vm64check tests to cover IMMU vm64
2023-04-07 21:14:52 -07:00
David Harris
25f394ce97
Fixed csrwrites.S to agree with ImperasDV. Now coverage tests pass iter-elf
2023-04-07 21:11:01 -07:00
David Harris
5c6d9f87a0
Fixed priv.S to initialize stimecmp and agree with ImperasDV
2023-04-07 20:44:01 -07:00
David Harris
7ad8d7f774
Bug fix: MTIME & MTIMEH registers are unimplemented and should fault when accessed
2023-04-07 20:43:28 -07:00
David Harris
8b4016582b
Fixed WALLY-init-lib to return correctly even from traps from compressed instructions
2023-04-07 20:24:33 -07:00
David Harris
982ade31c5
Fixed enabling machine timer interrupt
2023-04-06 22:18:33 -07:00
David Harris
c9887cb182
vm64 tests
2023-04-06 21:42:47 -07:00
David Harris
c24e81c57f
Division cleanup
2023-04-06 21:42:34 -07:00
David Harris
ce931d1fc5
Simplified integer division preprocessing in fdivsqrt
2023-04-06 16:43:28 -07:00
David Harris
f810ad3cec
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-04-06 14:07:59 -07:00
David Harris
1569bfbb98
Removed redundant stall signal to get spill coverage
2023-04-06 14:07:50 -07:00
Ross Thompson
87a1d12c3b
Merge branch 'main' of github.com:ross144/cvw
2023-04-06 15:33:24 -05:00
Ross Thompson
b57566e632
Added Jacob's ILA script.
2023-04-06 15:32:36 -05:00
Ross Thompson
fe922c8fac
Fixed syntax error.
2023-04-06 15:10:55 -05:00
Ross Thompson
270b3371f1
Added note about strange vivado behavior not inferring block ram.
2023-04-06 15:09:35 -05:00
Ross Thompson
d121364997
Similifed the no byte write enabled version of the sram model.
2023-04-06 14:18:41 -05:00
Kevin Thomas
1931859c45
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-04-06 12:38:41 -05:00
David Harris
fddbd79209
Update dvtestplan.md
2023-04-06 09:29:47 -07:00
