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Author SHA1 Message Date
Limnanthes Serafini
7d274eae74 Fix of InvalDelayed warning 2023-04-13 16:53:36 -07:00
David Harris
11434f05e2 Starting fdivsqrt cleanup 2023-04-13 16:53:33 -07:00
Sydeny
2b8891cefd Updating changes to fctrl.sv to reach 100% coverage. Excluding un-used sources of instructions for the ifu. 2023-04-13 16:27:53 -07:00
Ross Thompson
777edb0fcd Progress on arty a7 board. 2023-04-13 17:57:12 -05:00
David Harris
7ef57b77b9 Merge pull request #241 from Dygore/main 
Added a test for denormalized FP numbers
 2023-04-13 15:31:50 -07:00
Noah Limpert
a0a9d35d19 update tests.vh, add tlbKP to load all lines of tlb 2023-04-13 15:13:55 -07:00
Dygore
4854e09124 Added a test for denormalized FP numbers 2023-04-13 16:39:27 -05:00
Noah Limpert
276ce87582 Merge branch 'main' of https://github.com/openhwgroup/cvw into main 
pull in changes to trap handler so that permissions should change correctly
 2023-04-13 12:34:27 -07:00
David Harris
4281ee840c Merge pull request #239 from ACWright256/main 
Fixed exception handling to handle ecalls properly
 2023-04-13 09:32:56 -07:00
Alexa Wright
23d0d45bf6 Fixed exception handling to handle ecalls properly 2023-04-13 09:23:32 -07:00
Sydeny
42f6f79063 Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-04-12 16:20:50 -07:00
Alec Vercruysse
680aee7e07 Merge branch 'main' into coverage3 2023-04-12 16:00:15 -07:00
Alec Vercruysse
ad0e366766 track GetLinenum.do (tcl procedure to find line numbers to exclude) 2023-04-12 15:58:38 -07:00
Alec Vercruysse
01f2417524 cachefsm exclude icache logic without code reuse 2023-04-12 15:57:45 -07:00
Ross Thompson
04c90ac3d1 Merge pull request #236 from stineje/main 
Modification to testfloat.do
 2023-04-12 17:40:04 -05:00
James E. Stine
bc5c8adfb2 Add simple example based on original C program built by David Harris for OSU who want to see easy way to convert FP numbers 2023-04-12 17:20:11 -05:00
Alec Vercruysse
cc3b2bf435 Cachefsm gate LRUWriteEn with ~FlushStage 2023-04-12 13:32:36 -07:00
Sydeny
f9566299a0 fctrl coverage at 100% after removing redundancies from conditional statements 2023-04-12 13:07:30 -07:00
James E. Stine
001a364d6c Modification to testfloat.do to accept argument for nowave or by default none 2023-04-12 14:49:40 -05:00
Ross Thompson
10be07857c Merge pull request #229 from davidharrishmc/dev 
Turned on SVADU_SUPPORTED in rv32/64gc wally-config and in imperas.ic…
 2023-04-12 12:21:03 -05:00
Alec Vercruysse
1cb6e1751b Merge branch 'main' into coverage3 2023-04-12 09:34:09 -07:00
David Harris
6b05a71152 Removed unnecessary start term from initialization muxes to simplify and improve coverage 2023-04-12 03:34:01 -07:00
David Harris
7fd9b08c12 Merge pull request #234 from AlecVercruysse/cachesim 
CacheSim: Logger improvements, performance logging, sim wrapper
 2023-04-12 03:14:03 -07:00
Limnanthes Serafini
3f9a22e8d4 Minor comments. 2023-04-12 02:57:42 -07:00
David Harris
e6cb928ab2 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-04-12 02:57:33 -07:00
Limnanthes Serafini
095f3d5542 Added performance and distribution to sim and wrapper. Added colors too! 2023-04-12 02:54:05 -07:00
David Harris
463a1e2b33 Fixed fdivsqrt to avoid going from done to busy without going through idle first 2023-04-12 02:48:40 -07:00
David Harris
bedb3f95eb Swapped in svadu mmu tests 2023-04-12 02:06:52 -07:00
Limnanthes Serafini
65d29306ef Merge branch 'openhwgroup:main' into cachesim 2023-04-12 01:34:45 -07:00
Alec Vercruysse
0ed3e80ee0 only assign ClearDirtyWay for read-write caches 2023-04-12 01:15:35 -07:00
Alec Vercruysse
4cbb9bcec6 refactor cachefsm to get full coverage 
I had to exclude i$ states in coverage-exclusions-rv64gc.do,
but it's referred to by scope, which should be pretty robust
 2023-04-12 01:15:35 -07:00
Alec Vercruysse
a1bbcd5e8a Coverage and readability improvements to LRUUpdate logic 
The genvar stuff was switched to readable names to make it easier
to understand for the first time. In the LRUUpdate logic for loop,
a special case was added for simpler logic in the case of the root
node, to hit coverage.
 2023-04-12 01:15:35 -07:00
Alec Vercruysse
5b8c6f070e Make AdrSelMux and CacheBusAdrMux mux2 if READ_ONLY_CACHE 
Some address options are only used in the D$ case.
 2023-04-12 01:15:35 -07:00
Alec Vercruysse
7c9f68e984 Remove FlushStage Logic from CacheLRU 
For coverage.

LRUWriteEn is gated by FlushStage in cache.sv,
so removing the signal completely avoids future confusion.

Update cache.sv to reflect cacheLRU edit.
 2023-04-12 01:15:35 -07:00
Alec Vercruysse
68a01cb0f8 Exclude (FlushStage & SetValidWay) condition for RO caches 
Spent a long time trying to find a way to see if this condition was
possible, only to become relativly convinced that it isn't.
Basically, since RO cache writes only happen after a long period of
stall for the bus access, there's no way a flushD can be active
at the same time as a RO cache write. TrapM causes a FlushD, but
interrupts are gated by the "commited" logic and the exception
pipeline stalls.

I feel like its worth keeping the logic to be safe
so I've chosen to exclude it rather than explicitely remove it.
 2023-04-12 01:15:35 -07:00
Ross Thompson
18ad6455d0 Merge pull request #232 from stineje/main 
Mod testing for TestFloat
 2023-04-11 23:22:59 -05:00
James Stine
744e170be3 Add feature in testfloat.do to elect wave or nowave 2023-04-11 22:35:04 -05:00
James Stine
811004ef9f Update testbench-fp to run TestFloat for all FP operations 2023-04-11 22:16:20 -05:00
Limnanthes Serafini
a6545a0f47 Logger significantly improved. 2023-04-11 19:29:51 -07:00
Limnanthes Serafini
e5ead0f5b8 Minor logic cleanup (will elaborate in PR) 2023-04-11 19:29:39 -07:00
Limnanthes Serafini
e6a9d236b5 Wrapper for running CacheSim on the rv64gc suites 2023-04-11 19:29:05 -07:00
Limnanthes Serafini
926ec56e18 Cleanup + success message added to CacheSim 2023-04-11 19:28:28 -07:00
David Harris
26fbd3fdb0 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-04-11 19:08:09 -07:00
David Harris
0eb2511c35 Merge pull request #231 from kipmacsaigoren/priv-tests 
Priv tests Updates for SVADU, and SAIL
 2023-04-11 19:07:13 -07:00
Kip Macsai-Goren
34200e8c76 restored original virt mem tests when svadu is not supported 2023-04-11 18:47:08 -07:00
Kip Macsai-Goren
c4766c8a02 renamed virt mem tests to include svadu 2023-04-11 18:46:37 -07:00
Kip Macsai-Goren
b2d6084eea removed unnecessary 'deadbeef's at the end of reference outputs 2023-04-11 18:32:04 -07:00
Kip Macsai-Goren
a82c0a7780 Modified virt mem tests to do correct r/w when svadu is enabled 2023-04-11 18:08:30 -07:00
Kip Macsai-Goren
4aed880757 enabled SVADU for rv32/64gc 2023-04-11 17:42:26 -07:00
Kip Macsai-Goren
e0b938b409 Removed Trap outputs from writes covered by SVADU 2023-04-11 17:41:57 -07:00