3 Commits

Author	SHA1	Message	Date
Ross Thompson	9070b4adf5	OMG. the ddr3 has it's own mmcm (pll) which had incorreclty specified the input clock period as 3000 ps rather than 6000 ps so the pll was running at twice the speed. I speed the whole weekend on this. :(	2023-04-17 11:10:19 -05:00
Ross Thompson	5da5b76449	Fixed more issues with arty a7 constarints.	2023-04-16 13:25:02 -05:00
Ross Thompson	c9445384d7	Realized we need a separate mmcm when using the mig 7 for ddr3 rather than the ddr4 mig. Go figure.	2023-04-14 18:02:16 -05:00