11 Commits

Author	SHA1	Message	Date
David Harris	b911056e66	Changed Wally to CORE-V Wally	2023-01-11 14:03:44 -08:00
David Harris	e92cffbb5e	Changed MIT license to Solderpad License	2023-01-10 11:35:20 -08:00
David Harris	9bdf79bfe6	Removed unused signals; added check for atomic in pmachecker	2023-01-07 05:59:56 -08:00
Ross Thompson	cabcb5e89e	Modified the LSU and IFU to allow concurrent DTIM/DCACHE+BUS and IROM/ICACHE+BUS. ... Don't use this commit as the rv32i tests are not passing.	2022-10-05 14:51:02 -05:00
Ross Thompson	122c88ee46	Created two new pma regions for dtim and irom.	2022-08-28 13:50:50 -05:00
Ross Thompson	5e63af5887	Reordered the adrdecs.	2022-08-28 13:38:57 -05:00
David Harris	f2517f8290	Preliminary work to make DTIM and Bus compatible. Not yet working because accesses to bus are causing illegal address faults on the bus.	2022-08-27 20:31:09 -07:00
David Harris	f0b4f69b65	Added IROM and DTIM decoding to adrdecs	2022-08-26 20:45:43 -07:00
Ross Thompson	1bb8d36308	Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault.	2022-01-27 17:11:27 -06:00
David Harris	3d2671a8b0	Reformatted MIT license to 95 characters	2022-01-07 12:58:40 +00:00
David Harris	115287adc8	Renamed wally-pipelined to pipelined	2022-01-04 19:47:41 +00:00