Ross Thompson
b4338a5a50
Modified the testbench to not use the loggers for unsupported configurations.
2023-03-28 16:27:54 -05:00
David Harris
5e352bf72e
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-03-28 14:27:08 -07:00
Ross Thompson
6b58cb8d65
Merge branch 'main' of github.com:ross144/cvw
2023-03-28 16:22:26 -05:00
Ross Thompson
34dd2850e0
Disable loggers by default.
2023-03-28 16:20:45 -05:00
Ross Thompson
cef75cfe06
Now reports if there is a hit or miss.
2023-03-28 16:20:14 -05:00
Ross Thompson
a48049f6fe
Restored performance counter reports.
2023-03-28 16:15:05 -05:00
Ross Thompson
7cc8d4f20c
Now have logging of i/d cache addresses, but the performance counter reports are x's.
2023-03-28 16:09:54 -05:00
Ross Thompson
f2edf0ff86
Merge branch 'main' of github.com:ross144/cvw
2023-03-28 14:47:16 -05:00
Ross Thompson
69f6b291c6
Possible fix for issue 148.
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I found the problem. We use a Committed(F/M) signal to indicate the IFU or LSU has an ongoing cache or bus transaction and should not be interrupted. At the time of the mret, the IFU is fetching uncacheable invalid instructions asserting CommittedF. As the IFU finishes the request it unstalls the pipeline but continues to assert CommittedF. (This is not necessary for the IFU). In the same cycle the LSU d cache misses. Because CommittedF is blocking the interrupt the d cache submits a cache line fetch to the EBU.
I am thinking out loud here. At it's core the Committed(F/M) ensure memory operations are atomic and caches don't get into inconsistent states. Once the memory operation is completed the LSU/IFU removes the stall but continues to hold Committed(F/M) because the memory operation has completed and it would be wrong to allow an interrupt to occur with a completed load/store. However this is not true of the IFU. If we lower CommittedF once the operation is complete then this problem is solved. The interrupt won't be masked and the LSU will flush the d cache miss.
This requires a minor change in the cachebusfsm and cachefsm. I will report back after I've confirmed this works.
2023-03-28 14:47:08 -05:00
Kevin Kim
adabb7c236
comment formatting
2023-03-28 11:40:19 -07:00
Kevin Kim
4c9670a082
Merge branch 'openhwgroup:main' into bitmanip_cleanup
2023-03-28 11:31:18 -07:00
David Harris
f0cab709f2
Added support (untested) for half and quad conversions
2023-03-28 10:53:06 -07:00
David Harris
40311c4f62
fixed fp->fp conversions
2023-03-28 10:35:41 -07:00
David Harris
e5955c5dd8
support more fp -> fp conversions
2023-03-28 10:28:01 -07:00
David Harris
fd2d08f501
Fixed fmv decoder
2023-03-28 10:21:33 -07:00
Ross Thompson
d55b0c8c1f
Merge pull request #169 from davidharrishmc/dev
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PMP Fix to issue 132
2023-03-28 11:49:00 -05:00
David Harris
82ae3a74e2
Fixed bitrot in testfloat tests
2023-03-28 09:35:19 -07:00
David Harris
20d8c2476e
Moved rv32 peripheral tests using TEST-LIB to wally32priv because rv32imc doesn't support PMP
2023-03-28 09:08:48 -07:00
David Harris
aa31b45d88
Fixed RV32 tests after PMP fix
2023-03-28 08:35:23 -07:00
David Harris
39d3bf8e8a
Fixed PMP issue 132. Updated tests to initialize PMP before using. Needs to remake tests
2023-03-28 06:58:17 -07:00
David Harris
01113320f4
Set PMP to allow all user/supervisor accesses in WALLY-init-lib
2023-03-28 06:46:11 -07:00
David Harris
f12fd30117
Merge pull request #168 from AlecVercruysse/makecoverage
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Add tests/coverage/ tests as a target to sim/Makefile
2023-03-28 05:23:04 -07:00
David Harris
8093f55e34
Merge pull request #167 from ross144/main
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Added clarificaiton to buildroot linux testvector generation
2023-03-28 05:21:44 -07:00
David Harris
20ebf7e536
CSRS privileged coverage test
2023-03-28 04:37:56 -07:00
Ross Thompson
108ad671cf
Now reports i cache and d cache memory accesses.
2023-03-27 23:44:50 -05:00
Ross Thompson
ba2b022653
Merge pull request #166 from magpyed/patch-1
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Fixing order of local repo commands in README
2023-03-27 22:41:20 -05:00
Ross Thompson
5844ba8e71
Merge branch 'main' of github.com:ross144/cvw
2023-03-27 18:37:07 -05:00
Ross Thompson
510a0bb3ba
First stab at the i cache logger.
2023-03-27 18:36:51 -05:00
Ross Thompson
498a17deda
Added some additional details about the buildroot install.
2023-03-27 18:06:20 -05:00
Alec Vercruysse
a0aac6b15c
add tests/coverage/ tests as a target to sim/Makefile
2023-03-27 14:02:30 -07:00
Limnanthes Serafini
dd503c22ea
Fixing order of local repo commands in README
2023-03-27 13:35:48 -07:00
David Harris
2ad5547aa5
Merge pull request #163 from ross144/main
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updated GPIO signal names to match book.
2023-03-27 12:47:00 -07:00
Ross Thompson
4e2131066d
Added buildroot instructions back to readme. moved these instructions to the docs directory.
2023-03-27 14:45:55 -05:00
Ross Thompson
8504774a11
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-03-27 11:55:19 -05:00
Ross Thompson
3f1bf7bece
Merge pull request #165 from davidharrishmc/dev
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Imperas linux merge
2023-03-27 11:54:30 -05:00
David Harris
edaa306240
Removed unnecessary monitor
2023-03-27 09:52:38 -07:00
Ross Thompson
88c572d9bb
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-03-27 10:22:48 -05:00
David Harris
86ab90d715
Commented out setting RISCV in run-imperas-linux.sh
2023-03-27 06:34:45 -07:00
David Harris
f80abb9a75
Merge pull request #164 from eroom1966/add-linux
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Add linux
2023-03-27 06:26:41 -07:00
eroom1966
e65cbc6636
update to allow running of ImperasDV with linux boot
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optimize performance of the tracer
2023-03-27 09:46:16 +01:00
Lee Moore
39ac6be103
Merge branch 'openhwgroup:main' into add-linux
2023-03-27 09:44:13 +01:00
Kevin Kim
f3edbcea15
removed unnecessary signal indices
2023-03-26 20:06:55 -07:00
Kevin Kim
b4d6021b3b
removed unneccesary input signal from zbb
2023-03-26 19:39:49 -07:00
Ross Thompson
c8baffba7c
Started constrains file for arty a7 fpga.
2023-03-24 20:38:13 -05:00
Ross Thompson
3fc0c4b34e
Modified plic and uart to remove async reset. This removes vivado critical warning.
2023-03-24 20:37:48 -05:00
Ross Thompson
c10d98b1c8
Updated fpga constraints to remove critical warning.
2023-03-24 19:09:36 -05:00
Ross Thompson
78ab9f59af
Updated GPIO signal names to reflect book.
2023-03-24 18:55:43 -05:00
Ross Thompson
1f37e6dcea
Renamed controllerinputstage to controllerinput to match book.
2023-03-24 17:57:02 -05:00
Ross Thompson
fef025cb91
Merge pull request #162 from davidharrishmc/dev
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Merging spaces
2023-03-24 17:49:26 -05:00
David Harris
0dc6f9b991
Merged ross's spacing fixes
2023-03-24 15:47:26 -07:00
