David Harris
096242a6d8
Merged TIM and regular testbenches. RV32e now working and back in regression.
2022-02-08 12:18:13 +00:00
bbracker
fc2e3d1fbf
remove rv32e from regression because it is broken; goes with previous commit
2022-02-05 23:05:21 +00:00
David Harris
0dd8c719ad
Modified regression to use proper rv32e test name, but rv32e_wally32e still isn't passing due to loop exceeding iteration limit
2022-02-05 05:35:51 +00:00
David Harris
581fbb7d13
Modified wally-pipelined-batch.do to handle buildroot
2022-02-05 05:07:07 +00:00
David Harris
16b5fee795
RV32e tests
2022-02-04 14:30:36 +00:00
David Harris
1c049f1f67
renamed configs
2022-02-03 23:36:41 +00:00
Ross Thompson
41978d59e4
Quick patch to regression-wally to "fix" rv32ic.
2022-02-02 19:24:24 -06:00
David Harris
761dae72fe
Config file & wally-riscv-arch-test cleanup
2022-02-02 16:35:52 +00:00
Ross Thompson
d38ab9d2d7
Increased number of concurrent tests.
2022-01-27 08:45:25 -06:00
Ross Thompson
b961b104e0
Added colors to regression script to make it easy to pick out success from fail.
2022-01-26 22:40:32 -06:00
Ross Thompson
23c4ba2777
1. Modified the cache so it can handle the reset delay internally. This removes the mux from the IFU.
...
2. Removed the write address delay from simpleram.sv
3. Fixed rv32tim and rv32ic mode to handle missalignment correctly.
4. Added imperas32i and imperas32c to rv32tim mode.
2022-01-26 18:23:39 -06:00
David Harris
b967bcede2
LSU Cleanup
2022-01-15 01:11:17 +00:00
Ross Thompson
ce937a35a8
Added tim only test to regression-wally. Minor cleanup to ifu.
2022-01-14 11:13:06 -06:00
David Harris
573ff47763
renamed regression-wally.py to regression-wally
2022-01-07 17:47:38 +00:00