eroom1966
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52ebac59b8
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remove volatile for FFLAGS and FCSR
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2023-01-18 13:33:57 +00:00 |
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Ross Thompson
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374f95ebf3
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Fixed the rvvi CSR write enable not synchronized with a valid instruction in the Writeback stage.
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2023-01-17 18:24:46 -06:00 |
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eroom1966
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cf3223df22
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refactor all rvvi into single initial block
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2023-01-17 13:01:01 +00:00 |
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eroom1966
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2ead2cdaf4
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Code refactor and addition of rvvi interface
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2023-01-17 12:47:38 +00:00 |
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Ross Thompson
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14ecaabbf6
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Nearly complete RVVI tracer.
Missing PMP registers and performance counters other than MCYCLE and MINSTRET.
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2023-01-12 18:43:39 -06:00 |
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Ross Thompson
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0ea0e7a9e1
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rvvi trace is coming alone nicely.
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2023-01-12 14:46:31 -06:00 |
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Ross Thompson
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9a180f88f7
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Completely stripped down imperas simulation.
run with
vsim -c -do "do wally-pipelined-imperas.do rv64gc"
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2023-01-12 12:48:38 -06:00 |
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Ross Thompson
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5112ffcbc9
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Stripped out all signature checking.
Removed multiple tests loop.
Only runs 1 test now.
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2023-01-12 12:45:44 -06:00 |
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Ross Thompson
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8ee80c5d54
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Created separate imperas testbench.
Resolved logger issue with the duplicated instructions after commit.
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2023-01-12 12:07:07 -06:00 |
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Ross Thompson
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f59e1d03fc
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Added instruction logger.
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2023-01-12 10:09:34 -06:00 |
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