9 Commits

Author	SHA1	Message	Date
Kunlin Han	8c67a76912	Remove all #delay from non-testbench.	2024-03-13 10:31:40 -07:00
David Harris	45e2317636	Added Wally github address to header comments	2024-01-29 05:38:11 -08:00
Rose Thompson	ff5554ca61	Atomics work correctly without a d cache.	2024-01-16 10:43:20 -06:00
Rose Thompson	dfe5ef4427	Added logic for the non-cache atomics.	2024-01-15 17:47:17 -06:00
Rose Thompson	82a786f185	Hmm. Verilator is complaining about the parameter width. I'm not sure why so I changed to 1 bit.	2024-01-15 17:36:01 -06:00
Rose Thompson	614a83331f	Fixed part of issue #405. ... The non-cache version of the bus controller did not have the correct supression of BusCommitted for a read only controller.	2024-01-15 17:29:00 -06:00
Ross Thompson	1299319d0b	More parameterization. Based on Lim's work. EBU, IFU (except bpred), and IEU done.	2023-05-24 14:56:02 -05:00
Ross Thompson	b518177a45	Updated EBU to replace tabs with spaces.	2023-03-24 15:01:38 -05:00
David Harris	78eb90715c	Removed pipelined level of hierarchy	2023-02-02 14:14:11 -08:00