Katherine Parry
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03d823f5d7
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added fld in rv32 - needs testing
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2022-06-20 22:53:13 +00:00 |
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James Stine
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46bf9c351c
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Update C program for r=4 division by recurrence to match Table in EL
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2022-06-20 11:32:40 -05:00 |
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Daniel Torres
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d23df0bde8
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graph generator now generates 4 graphs, with space for 4 more
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2022-06-17 21:28:28 -07:00 |
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Daniel Torres
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397783812d
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embench and testbench now support running both O2 and Os build variations without overwriting one another
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2022-06-17 21:15:42 -07:00 |
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Daniel Torres
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196b43d113
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-06-17 20:53:19 -07:00 |
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Daniel Torres
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1d4c543f71
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arch tests now run on spike and sail and compare signatures during build
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2022-06-17 20:53:15 -07:00 |
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Madeleine Masser-Frye
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f807c70cdc
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
removing runArchive and plots directories from synthDC history
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2022-06-18 00:13:30 +00:00 |
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Madeleine Masser-Frye
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b538feb228
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Create test2
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2022-06-17 23:22:04 +00:00 |
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Daniel Torres
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6f381171de
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-06-17 15:50:10 -07:00 |
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Daniel Torres
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0ede7c412e
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removed old code from makefile, simplified code in testbench
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2022-06-17 15:13:38 -07:00 |
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Daniel Torres
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475220a5ff
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arch bug fixes and testbench changes
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2022-06-17 15:07:16 -07:00 |
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Madeleine Masser-Frye
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59a514ae81
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remove run deletion with wally synthesis
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2022-06-17 19:45:38 +00:00 |
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Madeleine Masser-Frye
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dfae71066e
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error calculation function, fixed energy units
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2022-06-17 19:36:32 +00:00 |
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Madeleine Masser-Frye
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8449029bf3
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latest synths and synth script
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2022-06-17 19:34:58 +00:00 |
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David Harris
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a911077a01
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-06-17 15:45:24 +00:00 |
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Daniel Torres
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cd56d256ad
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added new work files to gitignore
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2022-06-16 18:06:25 -07:00 |
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Daniel Torres
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8b6b0009a6
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-06-16 18:05:18 -07:00 |
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Daniel Torres
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83cce676a0
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added files needed for arch to build
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2022-06-16 18:05:06 -07:00 |
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Katherine Parry
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2a8c17170c
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hopefully fixed lint error
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2022-06-17 00:14:39 +00:00 |
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Katherine Parry
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c9cbf6082d
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-06-15 22:58:42 +00:00 |
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Katherine Parry
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0ffaec850b
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postprocess out of fpu critical path
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2022-06-15 22:58:33 +00:00 |
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Madeleine Masser-Frye
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154a1c80c1
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-06-15 18:30:27 +00:00 |
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Madeleine Masser-Frye
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84256924e7
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cleanup, plots for paper
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2022-06-15 18:28:36 +00:00 |
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Madeleine Masser-Frye
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74c527a818
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fresh set of syntheses
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2022-06-15 18:26:16 +00:00 |
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James Stine
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c660403ff2
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Add back SV for integer division to use 8-bit CPA in qslc
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2022-06-15 11:46:39 -05:00 |
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James Stine
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a078015271
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Add r=4 C code
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2022-06-15 11:44:09 -05:00 |
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Katherine Parry
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08b2481917
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some synth fpu optimizations
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2022-06-14 23:58:39 +00:00 |
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David Harris
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f6e52c7f08
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Removed testbench.sv.bak
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2022-06-14 22:04:38 +00:00 |
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DTowersM
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97d4368780
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-06-14 17:08:48 +00:00 |
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DTowersM
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c0b9a1b24e
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fixed a typo in makefile
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2022-06-14 17:08:39 +00:00 |
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Katherine Parry
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8e19331ad5
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removed false critical path from fpu
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2022-06-14 16:50:46 +00:00 |
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Katherine Parry
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674c31ce59
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fixed acciedental critical path in FPU
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2022-06-14 00:02:38 +00:00 |
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DTowersM
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7c0f4dd954
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-06-13 23:34:35 +00:00 |
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DTowersM
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a229e0ee87
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fixed typo in git ignore
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2022-06-13 23:34:27 +00:00 |
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DTowersM
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12f465ea05
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added back the .git ignore and .git modules for the coremark directory, also added graphGen to the main repo
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2022-06-13 23:33:10 +00:00 |
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DTowersM
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39ed36d0ba
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added back working coremark in benchmarks/riscv64-bcoremarkdirectory, experimental simplifications are in benchmarkscoremark/ but this doesn't currently work (some type of c bug)
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2022-06-13 23:23:57 +00:00 |
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Katherine Parry
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5f7072bd96
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postprocessing unit created and passing all tests
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2022-06-13 22:47:51 +00:00 |
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David Harris
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802bfd74fb
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Cleanup on RAM module
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2022-06-13 19:37:43 +00:00 |
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David Harris
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3c44b5842b
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Typo in gpio reset
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2022-06-13 19:37:05 +00:00 |
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slmnemo
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3626d5880e
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-06-13 12:30:33 -07:00 |
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David Harris
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9e1ec0255f
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Removed SRT testvectors from repo
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2022-06-13 19:27:33 +00:00 |
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slmnemo
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05a217c7e7
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-06-13 12:27:23 -07:00 |
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slmnemo
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c5d2037a7f
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Merge branch 'cacheburstmode' into main.
Cache burst mode is now working! It also uses the new RAM.
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2022-06-13 12:26:18 -07:00 |
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slmnemo
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a21d731834
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Added more comments
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2022-06-13 12:26:08 -07:00 |
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David Harris
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9080e35e54
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-06-13 19:26:07 +00:00 |
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David Harris
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09d72a33c5
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Fixed XOR logic in GPIO
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2022-06-13 19:26:03 +00:00 |
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slmnemo
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9f4ca06f7f
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Added comment about name of LSUBusInit/Lock signal
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2022-06-13 10:56:02 -07:00 |
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slmnemo
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a79737e95b
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Removed irrelevant comments in ahblite and made it more clear when to use certain transmission signals
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2022-06-10 20:43:56 -07:00 |
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slmnemo
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d6a1ee1141
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Added comments to signals added so the bus is easier to analyze
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2022-06-10 20:30:04 -07:00 |
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slmnemo
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31852fdb19
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Fixed failed regression state by only enabling counting when doing cached operations
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2022-06-10 20:00:09 -07:00 |
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