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2,091 Commits 4 Branches 2 Tags 53 MiB
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552 Commits

Author SHA1 Message Date
Skylar Litz
a69ab3bd1b fix some interrupt timing bugs 2021-12-03 12:32:38 -08:00
Ross Thompson
755c3e6a4c Fixed buildroot to work with the fpga's merge. 2021-12-02 18:09:43 -06:00
Ross Thompson
74ffb48c0a Mostly integrated FPGA flow into main branch. Not all tests passing yet. 2021-12-02 18:00:32 -06:00
Ross Thompson
8e4eacc18e Merge branch 'main' into fpga 2021-11-29 10:10:37 -06:00
Ross Thompson
e43aa6ead4 Merge branch 'main' into fpga 2021-11-29 10:06:53 -06:00
bbracker
c5d393fbc6 UART hack now looks at physical addresses so that it isn't bamboozled by S-mode accesses 2021-11-25 11:01:59 -08:00
bbracker
d90d708cf9 activate STVAL for buildroot 2021-11-21 10:40:28 -08:00
David Harris
fb3f267645 Coremark Cleanup, trying compile from addins 2021-11-19 06:09:04 -08:00
David Harris
d243f4bcd1 Cleaning up CoreMark benchmark 2021-11-18 20:12:52 -08:00
David Harris
54fef3e2ca vert "Simplifying riscv-coremark" 
This reverts commit bdc212cf88.
 2021-11-18 18:40:13 -08:00
David Harris
bdc212cf88 Simplifying riscv-coremark 2021-11-18 17:15:40 -08:00
David Harris
b996598b37 CoreMark testing 2021-11-18 16:14:25 -08:00
David Harris
b49c419d0b Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-11-17 13:28:33 -08:00
Skylar Litz
e35faa9b8a fixed interrupt timing bug 2021-11-16 16:46:17 -08:00
David Harris
5a521e28ee Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-11-16 12:30:55 -08:00
bbracker
23bd24323b get current privilege level from GDB for checkpoints 2021-11-15 14:49:00 -08:00
Ross Thompson
b8572d6a2a Changed several things. 
Removed the need to use async flip flops in SDC.
Added arrs, a synchronizer for reset.
I think this works with the real FPGA hardware.
The last build did not include this arrs but it worked.
 2021-11-12 11:13:50 -06:00
Skylar Litz
99a15e7897 fix timing of delayed interrupt 2021-11-11 09:35:51 -08:00
David Harris
f96152fa31 bringing Coremark back to life 2021-11-10 12:43:31 -08:00
bbracker
24d3244cfe checkpoint MIDELEG support 2021-11-06 03:44:23 -07:00
bbracker
1d3d7cbe1e fix merge conflict 2021-11-05 23:42:15 -07:00
bbracker
3077769cbd checkpoints now use binary ram files 2021-11-05 22:37:05 -07:00
bbracker
e4cf044932 fix testbench interrupt timing 2021-11-02 21:19:12 -07:00
David Harris
910957704b Add3d wally32i test 2021-11-01 13:17:49 -07:00
David Harris
4b57af9cff PIPELINE test running 2021-11-01 12:44:35 -07:00
David Harris
c306884e2c Adding custom Wally test infrastructure 2021-11-01 08:48:46 -07:00
David Harris
e9244e7a85 Fixed exe2memfile parsing of weird line in arch64d test 2021-10-30 07:26:18 -07:00
David Harris
717f9d48e9 tesgen cleanup, added riscv-arch-test D tests 2021-10-29 22:31:48 -07:00
David Harris
e62b57e2c2 commented out some failing FPU tests 2021-10-27 11:27:34 -07:00
David Harris
9cfb8deaab Fixed FResultSelM to select proper flags 2021-10-27 11:02:42 -07:00
David Harris
0421b7af56 Changes for floating point sims 2021-10-27 10:37:35 -07:00
David Harris
7d516c65e7 commented out nonworking tests 2021-10-26 08:56:49 -07:00
David Harris
ca700610f8 removed referenc outputs 2021-10-26 08:51:49 -07:00
bbracker
f39a509b5b adapt testbench linux to use reset_ext 2021-10-25 13:26:44 -07:00
bbracker
2c9c9328a9 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-25 12:25:37 -07:00
bbracker
c61cbf9618 change CHECKPOINT to be a parameter (not a macro) so that do scripts can control it; clean up checkpoint initialization macros 2021-10-25 12:25:32 -07:00
Ross Thompson
f7583d0e0d Updated uncore to use sdc. 
Fixed bug with fence instruction not correctly clearing dirty bits in d cache.
 2021-10-25 14:07:44 -05:00
David Harris
47124f36c8 Added synchronizer to reset 2021-10-25 10:05:41 -07:00
bbracker
b51e4d504b some linux testbench cleanup 2021-10-25 10:04:30 -07:00
bbracker
eb9740bc31 manually resolved git merge conflicts in testbench linux after checkpointing 2021-10-24 15:02:19 -07:00
bbracker
dcd4d9dd9f add checkpointing to linux testbench 2021-10-24 06:47:35 -07:00
bbracker
f6911be937 add W stage signals to linux testbench 2021-10-23 14:00:53 -07:00
bbracker
3b63dde570 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-23 13:17:37 -07:00
bbracker
d6fb441666 add option for regression to do a partial execution of buildroot 2021-10-23 13:17:30 -07:00
David Harris
8b1dc81d34 more lsu/ifu lint cleanup 2021-10-23 12:00:32 -07:00
David Harris
8b854bb1c2 Cleaned up LINT erors 2021-10-23 06:28:49 -07:00
David Harris
5142bfd624 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-10-23 06:15:49 -07:00
David Harris
3407b63c8a Added -lint flag to vsim. Cleaned some lint errors. Moved lint-wally to regression directory for convenience. 2021-10-23 06:15:26 -07:00
Ross Thompson
6bad4058eb Merge branch 'main' into fpga 2021-10-22 16:09:16 -05:00
Katherine Parry
00cc1e0c5c put the FMA priority encoders into their own module 2021-10-22 10:03:12 -07:00