David Harris
d327ed494a
Started DV Test Plan
2023-04-17 10:18:06 -07:00
David Harris
b00b8ba366
merged coverage exclusions
2023-04-17 10:17:48 -07:00
Ross Thompson
0be81fdfc8
Lowered arty a7 clock frequency to 15Mhz to meet timing. can probalby go faster.
2023-04-17 12:16:31 -05:00
Ross Thompson
a7a362f82e
Finally got the arty a7 to build.
2023-04-17 11:54:22 -05:00
Ross Thompson
9070b4adf5
OMG. the ddr3 has it's own mmcm (pll) which had incorreclty specified the input clock period as 3000 ps rather than 6000 ps so the pll was running at twice the speed. I speed the whole weekend on this. :(
2023-04-17 11:10:19 -05:00
David Harris
171fc0ee7f
Merge pull request #248 from dherreravicioso/main
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Added test coverage for reads to HPM counters and coverage exclusions
2023-04-16 18:18:31 -07:00
Ross Thompson
5da5b76449
Fixed more issues with arty a7 constarints.
2023-04-16 13:25:02 -05:00
Diego Herrera Vicioso
34dd481f93
Added test coverage for reads to HPM counters and added exclusions for impossible cases in rv64gc
2023-04-15 23:13:39 -07:00
Ross Thompson
d2272c0620
Found and fixed the major architecture issue with the mig 7 used in the arty a7 board.
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mig 7 is completely different from the ddr4 mig in that the internal pll does not general the required clocks. An external mmcm is required to general two inputs clocks and the required user clock.
2023-04-15 11:13:28 -05:00
Sydeny
af51b6f16c
trimming comments on fctrl bug fixes
2023-04-15 00:48:32 -07:00
Ross Thompson
a77d403e4c
Merge pull request #233 from AlecVercruysse/coverage3
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Full I$ coverage
2023-04-14 22:15:11 -05:00
Alec Vercruysse
862d1e0116
replace instances of code duplication for i$ exclusions w/commands
2023-04-14 17:10:39 -07:00
Ross Thompson
c9445384d7
Realized we need a separate mmcm when using the mig 7 for ddr3 rather than the ddr4 mig. Go figure.
2023-04-14 18:02:16 -05:00
Ross Thompson
29146ac839
Merge pull request #247 from AlecVercruysse/code_quality
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Code Quality
2023-04-14 16:46:39 -05:00
Limnanthes Serafini
5952a4b0a3
Final small fix
2023-04-14 14:15:52 -07:00
Limnanthes Serafini
e20f00a520
Merge branch 'code_quality' of https://github.com/AlecVercruysse/cvw into code_quality
2023-04-14 14:14:40 -07:00
Limnanthes Serafini
34aedc4f79
indent fix
2023-04-14 14:14:34 -07:00
Limnanthes Serafini
1b8e9cd9ac
Merge branch 'openhwgroup:main' into code_quality
2023-04-14 14:13:15 -07:00
David Harris
afd2cc9c91
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-04-14 12:57:26 -07:00
Ross Thompson
1a77bd7554
Merge pull request #245 from Dygore/main
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Added Multiple tests to increase FPU Coverage
2023-04-14 14:51:28 -05:00
Dylan
8ee76174d7
Merge branch 'openhwgroup:main' into main
2023-04-14 14:41:26 -05:00
Dygore
92a0827d80
Added multiple tests to increase FPU coverage
2023-04-14 14:41:05 -05:00
Ross Thompson
b5799c896e
Finally fixed the ddr3 mig script to work correclty.
2023-04-14 11:41:51 -05:00
David Harris
f77fee605f
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
2023-04-14 04:16:11 -07:00
David Harris
e8d630d069
Merge pull request #244 from Dygore/main
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Added tests for full coverage of the FPU result sign module
2023-04-14 04:02:29 -07:00
Dylan
4c91bb3b76
Merge branch 'openhwgroup:main' into main
2023-04-14 00:36:57 -05:00
Dygore
23dbca3991
Added tests for full coverage of the FPU result sign module
2023-04-14 00:36:12 -05:00
Limnanthes Serafini
95223bf11c
More cleanup
2023-04-13 21:34:50 -07:00
Limnanthes Serafini
28dd41291a
More cleanup
2023-04-13 21:02:30 -07:00
Limnanthes Serafini
94b686fcf6
More changes
2023-04-13 21:02:15 -07:00
Limnanthes Serafini
5d12afa671
Some cleanup
2023-04-13 21:01:57 -07:00
Limnanthes Serafini
4ec28ef32d
Merge branch 'openhwgroup:main' into code_quality
2023-04-13 19:59:58 -07:00
Limnanthes Serafini
6fddc591b5
Finished up testbench reformatting
2023-04-13 19:18:26 -07:00
Limnanthes Serafini
99cd913d75
Further indents
2023-04-13 19:07:43 -07:00
Limnanthes Serafini
0862688168
testbench code visual improvements
2023-04-13 19:06:09 -07:00
David Harris
cfca584bc7
Merged coverage-exclusions
2023-04-13 18:15:23 -07:00
David Harris
fe083e1edc
Merge pull request #243 from Noah-G-L/main
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Pull Request to add tlbKP.S - Fill in cache lines
2023-04-13 18:13:04 -07:00
Noah Limpert
30ed9c2b69
add back K. Box and M. Cook Lsu test
2023-04-13 17:50:18 -07:00
Noah Limpert
187c5b07c7
make pull request more clean
2023-04-13 17:44:09 -07:00
Noah Limpert
c76de00d60
Revert "instantiate 5 4KiB arrays, aim to thrash all 4 ways"
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This reverts commit 0fea40282a
2023-04-13 17:40:39 -07:00
David Harris
2e568877b0
fdivsqrtfsm coverage attempt to waive a state
2023-04-13 17:40:14 -07:00
Noah Limpert
4ab27b4f12
Revert "Test File for Pull Request, Attempt to fill all four ways"
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This reverts commit f770243689
2023-04-13 17:28:37 -07:00
David Harris
b378001213
Merge pull request #237 from SydRiley/main
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fctrl coverage at 100% after removing redundancies from conditionals
2023-04-13 17:10:46 -07:00
David Harris
1c9c94563d
Merge pull request #242 from AlecVercruysse/cachesim
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InvalDelayed warning fix; Miscellaneous typo and indent cleanup
2023-04-13 17:07:47 -07:00
Noah Limpert
bcbbcd5a30
Merge branch 'main' of https://github.com/openhwgroup/cvw into main
2023-04-13 17:00:48 -07:00
Limnanthes Serafini
38349e6a4f
Merge branch 'cachesim' of https://github.com/AlecVercruysse/cvw into cachesim
2023-04-13 17:00:43 -07:00
Limnanthes Serafini
51f6561476
A couple indents->spaces
2023-04-13 17:00:41 -07:00
Noah Limpert
419377a8f8
git did not seem to add tests.vh, trying again
2023-04-13 16:59:10 -07:00
Limnanthes Serafini
1125bad9cb
Merge branch 'openhwgroup:main' into cachesim
2023-04-13 16:54:35 -07:00
Limnanthes Serafini
e33721fbe4
Merge branch 'cachesim' of https://github.com/AlecVercruysse/cvw into cachesim
2023-04-13 16:54:16 -07:00
