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2 Commits

Author SHA1 Message Date
Ross Thompson
517cae796c Fixed more constraint issues in fpga. 
Added back in the ILA.
Design does not work yet.  Stil having issues with order of automatic
clock and I/O constraint ordering.
Added back in the preload for the boottim.
 2021-12-05 15:14:18 -06:00
Ross Thompson
2a7467c76d Separated timing constraints from ILA. 2021-12-01 18:15:04 -06:00