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Author SHA1 Message Date
Ross Thompson
7c3d6bbdb4 Moved lsu virtual memory logic into separate module. 2022-01-31 11:56:03 -06:00
Ross Thompson
e35a8299ec Encapsulated dtim. 2022-01-31 11:23:55 -06:00
Ross Thompson
dbe40856a2 Removed unused signals in the LSU. 2022-01-31 10:35:35 -06:00
Ross Thompson
bfbc31d184 Moved atomic logic to own module. 2022-01-31 10:28:12 -06:00
Ross Thompson
ef770fd183 Encapsulated the bus data path into a separate module. 2022-01-31 10:15:48 -06:00
Kip Macsai-Goren
1077cf08b0 added machine info test that uses new test library 2022-01-31 05:54:43 +00:00
Kip Macsai-Goren
5386f1b4fa tentatively remade test lib to use macros for more flexibility 2022-01-31 05:54:43 +00:00
Kip Macsai-Goren
01d6c3a4b9 converted library to header file for RISCV test compliance 2022-01-31 05:54:43 +00:00
Kip Macsai-Goren
e3ea593ed8 updated tests to use test title instead of number encoding 2022-01-31 05:54:42 +00:00
James Stine
3f5f5e48fa Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-01-30 21:03:24 -06:00
James Stine
6c9b4f648c Change DC script to not do a full synthesis but partial synthesis until I configure to be more optimized 2022-01-30 21:02:41 -06:00
David Harris
2d112698b7 Replaced || and && with | and & 2022-01-31 01:07:35 +00:00
David Harris
c367d19fc6 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-01-31 00:59:49 +00:00
David Harris
ea85e185f1 gitmodules 2022-01-31 00:59:44 +00:00
James Stine
8db15aee31 Add synthesis using DC shell back into repository 2022-01-30 17:35:15 -06:00
James Stine
1080281cb2 Add synthesis using DC shell back into repository 2022-01-30 17:34:56 -06:00
Ross Thompson
d52c5b0393 LSU and IFU cleanup. 2022-01-28 15:26:06 -06:00
Ross Thompson
de0bef4f5b Updated wave.do to match the ifu/lsu changes. 2022-01-28 14:37:15 -06:00
Ross Thompson
147d71fd46 Clean up of mmu instances in IFU and LSU. 2022-01-28 14:02:05 -06:00
Ross Thompson
4a8d0cb981 Moved spills to own module. 2022-01-28 13:40:35 -06:00
Ross Thompson
7fedc6b878 Cleaned up the InstrMisalignedFault. 2022-01-28 13:19:24 -06:00
Ross Thompson
b621eb78fb Updated debug2 ila signal names. 2022-01-28 11:43:49 -06:00
James Stine
ef811c7786 Remove book_flow to add back later - will add synthDC back within 30m 2022-01-28 08:18:30 -06:00
David Harris
52b8b68086 Added math.h to fir.c 2022-01-28 00:26:06 +00:00
Ross Thompson
1bb8d36308 Moved all instr/load/storeamo faults to mmu with the exception of instr misaligned fault. 2022-01-27 17:11:27 -06:00
Ross Thompson
d7d7c1cb7d Relocated the misalignment faults. 2022-01-27 16:03:00 -06:00
David Harris
87aa0724a2 IFU cleanup 2022-01-27 17:18:55 +00:00
David Harris
218ff3e25d IFU cleanup 2022-01-27 16:41:57 +00:00
David Harris
1c22077841 Optimized out second adder from IFU for PC+2 2022-01-27 16:06:24 +00:00
David Harris
62e5c7fd13 Comments in LSU code about restructuring 2022-01-27 15:53:59 +00:00
Ross Thompson
9a9dfcae40 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-01-27 08:45:33 -06:00
Ross Thompson
d38ab9d2d7 Increased number of concurrent tests. 2022-01-27 08:45:25 -06:00
David Harris
975c0e72c8 Set up rv32emc config 2022-01-27 14:37:58 +00:00
David Harris
5eccbcf531 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-01-27 14:33:35 +00:00
David Harris
384cd0d092 Added synthesis submodules 2022-01-27 14:31:34 +00:00
Ross Thompson
aa474ad588 Added generated source code for the wally riscv arch tests rv32i_m and rv64i_m. 2022-01-27 08:11:46 -06:00
Ross Thompson
75c33bc6c9 BPPredWrongM needs to be 0 when there is no branch predictor. BPPredWRongM is only used when there is an icacheflush. 2022-01-27 07:59:59 -06:00
Ross Thompson
b961b104e0 Added colors to regression script to make it easy to pick out success from fail. 2022-01-26 22:40:32 -06:00
Ross Thompson
c3a78553be Removed mux in PCNextF logic. Minor IFU improvements. 2022-01-26 22:33:26 -06:00
Ross Thompson
23c4ba2777 1. Modified the cache so it can handle the reset delay internally. This removes the mux from the IFU. 
2. Removed the write address delay from simpleram.sv
3. Fixed rv32tim and rv32ic mode to handle missalignment correctly.
4. Added imperas32i and imperas32c to rv32tim mode.
 2022-01-26 18:23:39 -06:00
Ross Thompson
2c982dca03 IFU simplifications. 2022-01-26 13:54:59 -06:00
David Harris
0023c4cb57 Adjusted test cases for new GPIO base address 2022-01-26 19:15:48 +00:00
David Harris
c6adb7b6b1 Updated configs to fix GPIO address to match FU540 2022-01-26 18:16:34 +00:00
David Harris
c60bb68bff Testgen working for Lab 2 2022-01-26 18:01:51 +00:00
David Harris
492c1a488e Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2022-01-26 17:21:09 +00:00
David Harris
f90e58ff34 New testgen.py 2022-01-26 17:21:02 +00:00
bbracker
ea92cc3af2 a different approach to QEMU: add Wally as a completely new machine 2022-01-26 15:02:24 +00:00
Ross Thompson
728e46a794 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2022-01-25 19:21:04 -06:00
Ross Thompson
db197b6491 Added pin location for reset on VCU118 board. Somehow this was missing and still worked. 2022-01-25 17:48:42 -06:00
David Harris
1e533cdf25 Removed and restored embench-iot 2022-01-25 22:12:28 +00:00