Ross Thompson
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40b2f7ff9c
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Updated comments.
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2023-07-06 15:24:26 -05:00 |
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Ross Thompson
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dc50ddd75e
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Removed unused parameter.
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2023-07-06 14:57:07 -05:00 |
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Ross Thompson
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0394f3232f
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-07-06 14:55:43 -05:00 |
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Ross Thompson
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18278b7f4d
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It's a bit hacky, but the plic now passes the regression test and should be compatible with the fpga.
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2023-07-06 14:07:37 -05:00 |
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Ross Thompson
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ba9d5287d9
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This is at least functionally correct, but has verilator lint issues.
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2023-07-06 11:53:34 -05:00 |
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Ross Thompson
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930aed0898
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closer, but the wally32/64priv tests are failing.
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2023-07-05 17:47:38 -05:00 |
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Ross Thompson
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c0fdd3fbca
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Partially solved fpga boot.
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2023-07-05 17:30:55 -05:00 |
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David Harris
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19efc4eda8
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Fixed comment typo
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2023-07-04 11:34:58 -07:00 |
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David Harris
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4f07d89d74
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fixed spacing in fdivsqrt
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2023-07-04 11:27:36 -07:00 |
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David Harris
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e6ba362794
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Added prefetch instructions; sent cbo instructions to LSU
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2023-07-02 10:55:35 -07:00 |
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David Harris
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cc87317189
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Added prefetch signals
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2023-07-02 10:06:58 -07:00 |
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David Harris
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a5c6ae1f78
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Enhanced decoder to produce individual CMOpE output for the 4 CMO instructions
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2023-07-02 09:35:05 -07:00 |
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David Harris
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6a88ac28e4
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Fixed csr typos
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2023-07-02 02:01:40 -07:00 |
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David Harris
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96477a4879
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Fixed ENVCFG to reply on both MENVCFG and SENVCFG when in user mode
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2023-07-02 02:00:27 -07:00 |
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David Harris
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e2708534cd
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Added environment configuration control (menvcfg/senvcfg) of cbo instructions
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2023-07-02 01:52:25 -07:00 |
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David Harris
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4d1ddd0c91
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Gated floating-point load/stores with STATUS_FS and added initial decoding for Cache Management Operations
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2023-07-02 00:34:30 -07:00 |
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David Harris
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110dd42cfb
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improved decoder checking atomic and RW and MW and privileged instructions
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2023-07-02 00:02:03 -07:00 |
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David Harris
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07cf1dd9da
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improved decoder checking atomic instructions
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2023-07-01 23:10:57 -07:00 |
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David Harris
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e05288afd9
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Improved instruction decoding for illegal floating-point loads/stores and fences
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2023-07-01 22:48:04 -07:00 |
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Ross Thompson
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1d2eb60ffb
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-06-18 16:37:19 -05:00 |
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David Harris
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95960620a2
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Removed redundant and not-covered atomic check from StoreStallD
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2023-06-16 16:05:53 -07:00 |
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Ross Thompson
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2f35bec970
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FPGA synthesis is broken. This commit moves closer to fixing the issues causes by parameterization.
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2023-06-16 15:40:13 -05:00 |
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Ross Thompson
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6d31936e89
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Added comment to uart LCR to check reset value after updating FPGA.
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2023-06-15 15:39:51 -05:00 |
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Ross Thompson
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34d1d50b87
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-06-15 15:38:38 -05:00 |
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Ross Thompson
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a011b7d591
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Merge branch 'testbench-params2'
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2023-06-15 15:31:13 -05:00 |
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Ross Thompson
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a55bcad5c1
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-06-15 14:57:23 -05:00 |
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David Harris
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52ab586a9d
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Added input gating on FPU
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2023-06-15 12:38:33 -07:00 |
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David Harris
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524d8e8469
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Gated MDU to save power; doesn't seem to have affected simulation time
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2023-06-15 12:17:23 -07:00 |
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David Harris
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c7d06382b3
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Bit manipulation comment cleanup
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2023-06-15 12:16:46 -07:00 |
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Ross Thompson
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44c72c20e2
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Actually removed old `define configuration file for rv64gc. There were a lot of dangling problems.
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2023-06-15 14:05:44 -05:00 |
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David Harris
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33ff9766b4
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Gated inputs to BMU when inactive to save power and simulation time
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2023-06-15 11:56:59 -07:00 |
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Ross Thompson
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2fc8080102
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Got the srams parameterized correctly now.
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2023-06-15 13:42:24 -05:00 |
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David Harris
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e0b6a2d693
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Fixed UART merge conflict
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2023-06-15 11:36:37 -07:00 |
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Ross Thompson
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e431f90cf3
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Found a whole bunch of files still using the old `define configurations.
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2023-06-15 13:09:07 -05:00 |
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Harshini Srinath
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37c930bb27
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Update wallypipelinedsoc.sv
Program clean up
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2023-06-15 10:39:37 -07:00 |
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Harshini Srinath
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fd00067b7f
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Update wallypipelinedcore.sv
Program clean up
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2023-06-15 10:38:38 -07:00 |
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Harshini Srinath
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e3f8280ff9
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Update cvw.sv
Program clean up
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2023-06-15 10:29:33 -07:00 |
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Harshini Srinath
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e9cfbd95f4
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Update uncore.sv
Program clean up
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2023-06-15 10:23:47 -07:00 |
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Harshini Srinath
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5d8e120031
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Update uart_apb.sv
Program clean up
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2023-06-15 10:21:46 -07:00 |
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Harshini Srinath
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53ad51ae54
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Update uartPC16550D.sv
Program clean up
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2023-06-15 10:20:29 -07:00 |
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Harshini Srinath
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ae165b35f9
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Update rom_ahb.sv
Program clean up
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2023-06-15 10:13:15 -07:00 |
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Harshini Srinath
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97917c2a44
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Update ram_ahb.sv
Program clean up
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2023-06-15 10:10:38 -07:00 |
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Harshini Srinath
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a9495e8595
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Update plic_apb.sv
Program clean up
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2023-06-15 10:08:16 -07:00 |
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Harshini Srinath
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afa0bcdd16
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Update gpio_apb.sv
Program clean up
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2023-06-15 10:04:28 -07:00 |
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Harshini Srinath
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83acb77507
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Update clint_apb.sv
Program clean up
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2023-06-15 09:59:11 -07:00 |
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David Harris
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380c9e1dde
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-06-15 07:01:44 -07:00 |
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Ross Thompson
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6bb5f32eb9
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Improved simulation speed by gating bitmanip zbc's clmul's X and Y inputs with BSelect != 11. Reduced simulation time from 3m45s to 2m35s.
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2023-06-14 15:28:58 -05:00 |
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Harshini Srinath
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e0a30ecc22
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Merge branch 'main' into main
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2023-06-14 11:52:45 -07:00 |
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David Harris
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fe35f9ecdb
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Moved cvw.sv to src root directory to avoid double-compiling and producing a warning. Adjusted to files to reflect this.
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2023-06-14 09:44:52 -07:00 |
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David Harris
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59bf356064
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Removed *** from UART code
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2023-06-14 08:47:01 -07:00 |
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