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Author SHA1 Message Date
Ross Thompson
5e4e44a2cc Added patch file for the qemu modifications. 
Added instructions for building and installing qemu.
 2021-12-13 18:36:00 -06:00
Ross Thompson
b224fbb447 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-13 18:30:14 -06:00
Ross Thompson
0e9e561726 Updated .gitignore file to hide fpga outputs. 2021-12-13 18:30:10 -06:00
Ross Thompson
f061a26411 Cleaned up fpga synthesis script. 2021-12-13 18:26:54 -06:00
Ross Thompson
8c55bd7b7e Possible fix for icache and ptw interlock deadlock issue. 2021-12-13 18:23:43 -06:00
Ross Thompson
b9c8b808ea Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-13 17:16:20 -06:00
Ross Thompson
7d00649b61 Formating changes to cache fsms. 2021-12-13 17:16:13 -06:00
Ross Thompson
5361f69639 Fixed some typos in the dcache ptw interaction documentation. 2021-12-13 15:47:20 -06:00
David Harris
74cf0eb96a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-13 07:57:49 -08:00
David Harris
1ca949c0bb Simplified ALU and source multiplexers pass tests 2021-12-13 07:57:38 -08:00
kwan
5ede8126fd priviledge .* removed, passed regression 2021-12-13 00:34:43 -08:00
kwan
b05bc3c19e test 2021-12-13 00:31:51 -08:00
kwan
83dae9d774 priviledge .* fixed, passed local regression 2021-12-13 00:22:01 -08:00
Kevin
3aad1137c2 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-12 17:53:41 -08:00
Kevin
b928d01bb8 dot stars conversions on the rest of the testbenches 2021-12-12 17:53:26 -08:00
Ross Thompson
8e39034dbd Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-12 17:33:29 -06:00
Ross Thompson
2f282e5570 Revert "Privilige .*s removed" 
This reverts commit 471f267987.
 2021-12-12 17:31:57 -06:00
Ross Thompson
fdbb7b6ef3 Revert "Priviledged .* removed" 
This reverts commit 96ac298596.
 2021-12-12 17:31:39 -06:00
Ross Thompson
547093b705 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-12 17:21:51 -06:00
Ross Thompson
bb79f70a63 Modified FPGA to add additional signals to ILA. Created advanced trigger for ILA using vivado's tsm language. 2021-12-12 17:21:44 -06:00
Ross Thompson
e6f2a316c8 Missed constraints file for xilinx ILA. 2021-12-12 15:06:29 -06:00
Ross Thompson
b88ec949cf Added proper credit to Richard Davis, the author of the original sd card reader. 2021-12-12 15:05:50 -06:00
kwan
96ac298596 Priviledged .* removed 2021-12-12 09:55:45 -08:00
kwan
471f267987 Privilige .*s removed 2021-12-12 09:54:14 -08:00
David Harris
d3c3ab3e85 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-12 05:49:31 -08:00
Kevin
78fbe542a9 edited one testbench, yet to run regression 2021-12-10 20:26:20 -08:00
Ross Thompson
c688b27a20 Performance counters now output of coremark. 2021-12-09 14:48:17 -06:00
Ross Thompson
cd59809e42 Fixed numerous errors in the preformance counter updates. 
Fixed dcache reporting of access and misses.
Added performance counter tracking to coremark.
 2021-12-09 11:44:12 -06:00
bbracker
4bc4930ff3 fix recursive signal logging for graphical sims 2021-12-08 16:07:26 -08:00
bbracker
64652be7c5 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-08 14:12:18 -08:00
bbracker
c97e96f553 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-08 14:12:09 -08:00
bbracker
6a6835ddc3 fix release of ReadDataM 2021-12-08 14:11:43 -08:00
slmnemo
3ff994f50d Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 
help
 2021-12-08 14:09:58 -08:00
slmnemo
094f45e28b Removed .* from /wally-pipelined/src/uncore/uart.sv 2021-12-08 14:02:53 -08:00
Ross Thompson
a55018b67a Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-08 15:50:43 -06:00
Ross Thompson
3bdda9687a Fixed some issues with the SDC having a different counter. When this is copied into synthesis the file names where the same and it gave a conflict. 
Remove preload from dtim.
 2021-12-08 15:50:15 -06:00
David Harris
9e2c3bef3c Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-08 13:48:49 -08:00
David Harris
0b63c1cede Refactored IEU/ALU logic 2021-12-08 13:48:04 -08:00
Noah Limpert
e97dd080a0 updated fcmp.sv instantiation to remove x*'s 2021-12-08 13:34:33 -08:00
David Harris
a174c8b4d7 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-08 12:33:59 -08:00
David Harris
5d4014d351 Refactoring ALU and datapath muxes 2021-12-08 12:33:53 -08:00
Ross Thompson
37451b8978 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-08 13:40:44 -06:00
Ross Thompson
e1249f4312 Updated coremark testbench with the extra ports from FPGA merge. 
Fixed coremark Makefile to create work directory.
 2021-12-08 13:40:32 -06:00
bbracker
4060e77b56 increase regression's expectations of buildroot to 246 million 2021-12-08 07:01:22 -08:00
slmnemo
d58f318d39 Removed .*s from wally-pipelined/src/uncore/uncore.sv 2021-12-08 01:03:02 -08:00
slmnemo
52b4802600 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-08 00:26:13 -08:00
Noah Limpert
feb21d1c4a removed .* instantiation from ieu.sv and datapth.sv in ieu folder 2021-12-08 00:24:27 -08:00
slmnemo
acacd13ffc Removed .* from mmu instance inside lsu.sv. 2021-12-08 00:15:30 -08:00
Katherine Parry
d0e708f239 FMA uses one LOA 2021-12-07 14:15:43 -08:00
bbracker
d459e35645 undo intentionally breaking commit 2021-12-07 13:43:47 -08:00