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822e60bd3d
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61 Commits

Author SHA1 Message Date
Ross Thompson
822e60bd3d Found the coremark performance issue. The testbench was continuously forcing the BTB to all zeros. Once fixed it resolved the performance problem. 2023-06-05 15:42:05 -05:00
Ross Thompson
e56497101a Updated source code to be compatible with verilator 5.011 for lint only. 2023-05-31 10:44:23 -05:00
Ross Thompson
923c00b928 I think I've solved the slow down issue. Parameters can't be mixed with cvw_t and other types. 2023-05-26 13:56:51 -05:00
Ross Thompson
d47951fb51 The privileged unit is parameterized using Lim's method. 2023-05-26 12:03:46 -05:00
Ross Thompson
81b33fb48e Fixes load and store stall counters. 2023-05-22 10:08:49 -05:00
David Harris
e962e95e53 CSR code cleanup 2023-04-27 14:12:57 -07:00
David Harris
e69ebc45c0 Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-04-27 07:30:07 -07:00
Alexa Wright
79031e3de0 Added better comment for the exclusion in privdec.sv 2023-04-26 16:25:55 -07:00
Alexa Wright
55a74fd315 Excluded and added coverage for WFI test case. 2023-04-25 17:06:57 -07:00
David Harris
03448aa691 Commented about Sstvecd trap vector alignment 2023-04-24 12:20:33 -07:00
Diego Herrera Vicioso
c681789296 Excluded coverage for impossible cases in wficountreg and status.MPRV 2023-04-24 02:06:53 -07:00
David Harris
1d532dfcfc Fault on writes to odd-numbered PMPCFG in RV64 2023-04-22 15:32:39 -07:00
Diego Herrera Vicioso
34dd481f93 Added test coverage for reads to HPM counters and added exclusions for impossible cases in rv64gc 2023-04-15 23:13:39 -07:00
Limnanthes Serafini
c427b4c896 Misc typo and indent fixing. 2023-04-13 16:54:15 -07:00
Alexa Wright
34fd402f23 Excluded coverage for misaligned instructions 2023-04-10 23:18:25 -07:00
David Harris
7ad8d7f774 Bug fix: MTIME & MTIMEH registers are unimplemented and should fault when accessed 2023-04-07 20:43:28 -07:00
Ross Thompson
d1ac175e27 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-04-05 14:55:12 -05:00
Ross Thompson
7c2512446c Progress on bug 203. 2023-04-05 13:20:04 -05:00
David Harris
b7b1f2443f Fixed WFI to commit when an interrupt occurs 2023-04-04 09:32:26 -07:00
David Harris
b95730e3a1 Coverage improvements in ieu, hazard units 2023-03-31 08:33:46 -07:00
David Harris
77d5f1c81b Refactored InstrValidNotFlushed into CSR Write signals 2023-03-30 17:06:09 -07:00
David Harris
25cd1cc432 Started factoring out InstrValidNotFlushed from CSRs 2023-03-30 14:56:19 -07:00
Kip Macsai-Goren
94f03b0d78 unnecessary comments cleanup 2023-03-29 19:32:57 -07:00
Kip Macsai-Goren
da905b4eb9 Resolved ImperasDV receiving incorrect cause values 2023-03-29 15:04:56 -07:00
David Harris
de2a0da9e9 Reduced number of bits in mcause and medeleg registers 2023-03-29 07:02:09 -07:00
David Harris
20ebf7e536 CSRS privileged coverage test 2023-03-28 04:37:56 -07:00
David Harris
edaa306240 Removed unnecessary monitor 2023-03-27 09:52:38 -07:00
Lee Moore
39ac6be103
Merge branch 'openhwgroup:main' into add-linux 2023-03-27 09:44:13 +01:00
Ross Thompson
730f3ac84e Fixed all tap/space issue in RTL. 2023-03-24 17:32:25 -05:00
David Harris
99c471ccfe Added csrwrites.S test case for privileged tests 2023-03-23 10:55:32 -07:00
eroom1966
1c3c8be148 support linux 2023-03-22 17:10:32 +00:00
David Harris
c4c7f5378e Select original compressed or uncompressed instruction for MTVAL on illegal instruction fault 2023-03-22 06:29:30 -07:00
David Harris
32c54db595 Fix Issue #142: SCOUNTEREN powers up at 1 instead of 0 2023-03-22 04:41:57 -07:00
David Harris
77fb1b57f4 Fix Issue 145 2023-03-22 04:33:14 -07:00
David Harris
031cc6967a Fix Issue #120 about SIE/SIP being 0 unless MIDELEG bits are set. However, this fix breaks the wally32/64priv tests in regression. 2023-03-18 10:10:58 -07:00
David Harris
08ce265420 Replaced FenceM with InvalidateICacheM for event counting of fence.i 2023-03-18 09:24:31 -07:00
Ross Thompson
fa8a550e12 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-03-09 13:29:38 -06:00
Ross Thompson
6d2d7d181e Updated testbench to record coremark performance counters. 
Added comment about mtval probably not being correct for compressed instructions.
 2023-03-08 17:11:27 -06:00
Kip Macsai-Goren
0ba1a59a70 added reset values to stime and stimecmp registers 2023-03-04 15:06:15 -08:00
Ross Thompson
7dd8fa16c1 Renamed BTB misprediction to BTA. 2023-03-03 00:18:34 -06:00
Ross Thompson
bdab2c8506 Added divide cycle counter. 2023-03-02 23:59:52 -06:00
Ross Thompson
4b501f6e03 Added the i and d cache cycle counters. 2023-03-02 23:54:56 -06:00
Ross Thompson
b19d51b6a2 Added fence counter. 2023-03-02 23:29:20 -06:00
Ross Thompson
3dbfa96aef Added csr write counter, sfence vma counter, interrupt counter, and exception counter. 2023-03-02 23:21:29 -06:00
Ross Thompson
cf4d8e6bd0 Added store stall to performance counters. 2023-03-02 23:10:54 -06:00
Ross Thompson
e257ec96ac Reordered performance counters and added space for new ones. 2023-03-02 23:04:31 -06:00
Ross Thompson
3d1ffac7d7 Cleaned up branch predictor performance counters. 2023-03-01 17:05:42 -06:00
Ross Thompson
2773048bd4 Name cleanup. 2023-02-28 17:48:58 -06:00
Ross Thompson
8af61c0cc0 Name changes to reflect diagrams. 2023-02-28 15:37:25 -06:00
Ross Thompson
bb276da6eb Merge branch 'main' of https://github.com/openhwgroup/cvw into main 2023-02-26 12:06:06 -06:00