Ross Thompson
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1e83810450
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Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally.
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2021-03-30 23:18:20 -05:00 |
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Thomas Fleming
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89a2fe5741
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Finish finite state machines for page table walker
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2021-03-25 02:48:40 -04:00 |
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bbracker
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5327dcfcc8
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instrfaults not respecting stalls bugfix
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2021-03-25 00:16:26 -04:00 |
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Ross Thompson
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cdb7d15709
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Fixed bugs with the csr interacting with StallW. StallW is required to pervent updating a csr. Now have a working branch predictor and performance counters to track the number of commited branches and mispredictions.
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2021-03-24 15:56:55 -05:00 |
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Shreya Sanghai
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09b90557f7
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PC counts branch instructions
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2021-03-23 14:25:51 -04:00 |
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Shreya Sanghai
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dfc86539cc
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Merge branch 'gshare' into main
Conflicts:
wally-pipelined/regression/wave.do
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2021-03-18 17:25:48 -04:00 |
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Thomas Fleming
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062c4d40da
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Connect tlb, pagetablewalker, and memory
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2021-03-18 14:35:46 -04:00 |
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Shreya Sanghai
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23a7c8cd92
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made performance counters count branch misprediction
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2021-03-16 11:24:17 -04:00 |
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Thomas Fleming
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e48dc38869
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Export SATP_REGW from csrs to MMU modules
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2021-03-05 01:22:53 -05:00 |
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David Harris
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73920282af
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Eliminated flushing pipeline on CSR reads
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2021-02-26 17:00:07 -05:00 |
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David Harris
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cc42655789
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More memory interface, ALU testgen
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2021-02-15 10:10:50 -05:00 |
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David Harris
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429f48e766
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Rename ifu/dmem/ebu signals to match uarch diagram
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2021-02-02 15:09:24 -05:00 |
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David Harris
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bb83fda1d8
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Moved writeback pipeline registers from datapth into DMEM and CSR
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2021-02-02 13:02:31 -05:00 |
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David Harris
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92bf1674b4
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Moved fpu to temporary location to fix compile and cleaned up interface formatting
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2021-02-01 23:44:41 -05:00 |
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David Harris
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07af481b67
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Reorganized src hierarchically
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2021-01-30 11:50:37 -05:00 |
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