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1159 Commits

Author SHA1 Message Date
Ross Thompson
c33230d1c1 Fixed Bug 66. 
If a load missed at the same time as a spilled instruction fetch with an ITLB miss in the second cache line, the HPTW did not wait for the load miss to finish.
 2023-02-06 17:32:28 -06:00
Ross Thompson
4e8ef4a0ac Removed unreachable if branch in hptw next state logic. 2023-02-06 16:42:07 -06:00
David Harris
7cf98811f3 Parenthesized reduction operators to avoid DC lint 2023-02-04 18:49:47 -08:00
David Harris
43668a3fc5 Developing debug test 2023-02-04 08:31:47 -08:00
David Harris
6b9ae4fc89 Fixed merge issues on synthDC PR 2023-02-04 04:13:40 -08:00
David Harris
e831baf335 Improved illegal NaN-box detection and formatted fsgninj 2023-02-04 03:42:20 -08:00
David Harris
97ee3732fe Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-02-03 08:36:11 -08:00
David Harris
e6bfcd14fa Merged with memories 2023-02-02 14:50:46 -08:00
David Harris
78eb90715c Removed pipelined level of hierarchy 2023-02-02 14:14:11 -08:00