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Author SHA1 Message Date
Ross Thompson
aabb454d1c Added the i and d cache cycle counters. 2023-03-02 23:54:56 -06:00
Ross Thompson
cfca77172e Added fence counter. 2023-03-02 23:29:20 -06:00
Ross Thompson
f32f8c109a Added csr write counter, sfence vma counter, interrupt counter, and exception counter. 2023-03-02 23:21:29 -06:00
Ross Thompson
a313b10912 Added store stall to performance counters. 2023-03-02 23:10:54 -06:00
Ross Thompson
2dd693a3b3 Reordered performance counters and added space for new ones. 2023-03-02 23:04:31 -06:00
Ross Thompson
724f2634c5 Fixed bug in performance counter script. 2023-03-02 22:32:13 -06:00
Ross Thompson
1f3639bff6 Added support for branch target buffer stats. 2023-03-02 22:16:30 -06:00
David Harris
316b8b2250 Refactored Floating point division special case detection to avoid spurious trigger on Y for sqrt) 2023-03-02 20:00:47 -08:00
Kevin Kim
b21ca2fba0 bug fix, more elegant logic changes in controller 2023-03-02 16:00:56 -08:00
Kevin Kim
c9bd37c92b formatting 2023-03-02 15:28:43 -08:00
Kevin Kim
910eeea3ff removed main instruction decoder dependence on bmu controller 2023-03-02 15:28:33 -08:00
Kevin Kim
05b329dd6a added bitmanip illegal instruction signal 2023-03-02 15:09:55 -08:00
Kevin Kim
3e8e633a56 zbc comments 2023-03-02 13:52:00 -08:00
Kevin Kim
b0307f5082 formatted bmu decoder 2023-03-02 13:45:15 -08:00
Kevin Kim
24b0b83d52 moved ALUControlD into configurable block 2023-03-02 12:17:03 -08:00
Kevin Kim
0f60505179 moved SubArith and RegWriteE into configurable block 2023-03-02 12:15:57 -08:00
Kevin Kim
b81a5e4452 added BRegWriteE signal 2023-03-02 12:15:22 -08:00
Kevin Kim
5e10720bed rename shifternew to shifter 2023-03-02 11:45:32 -08:00
Kevin Kim
cf324510f3 zbc input select mux optimize 2023-03-02 11:43:05 -08:00
Kevin Kim
657719220a zbc select mux optimization 2023-03-02 11:40:29 -08:00
Kevin Kim
e62a752522 fixed controller lint, changed byte unit mux select name and input width 2023-03-02 11:36:12 -08:00
Kevin Kim
a5e2e24320 removed redundant zbs 2023-03-02 11:22:09 -08:00
Ross Thompson
9bd6851ed5 Merge pull request #123 from eroom1966/main 
fix the memory map privileges in the REF model view
 2023-03-02 09:27:35 -06:00
eroom1966
fe4d9d3e37 fix the memory map privileges in the REF model view 2023-03-02 15:25:27 +00:00
Ross Thompson
b98e007a53 Cleaned up branch predictor performance counters. 2023-03-01 17:05:42 -06:00
David Harris
5c8c50adba Merge branch 'main' of https://github.com/openhwgroup/cvw into dev 2023-03-01 11:18:05 -08:00
David Harris
23775c6d67 Renamed I/D TLBMissOrDAFault to TLBMissOrUpdateDA for consistency with UpdateDA 2023-03-01 11:18:00 -08:00
David Harris
a7b15c4503 Merge pull request #121 from ross144/main 
Branch predictor cleanup.  Chapter 10 now matches the hardware
 2023-03-01 09:57:59 -08:00
Ross Thompson
90b2f0a652 Set bp to use instruction class prediction by default. 2023-03-01 11:52:42 -06:00
Ross Thompson
dea6b643a6 Branch predictor cleanup. 
I think Ch 10 is now done except for BTB performance analysis and the section on running benchmarks and collecting data.
 2023-03-01 11:24:24 -06:00
Ross Thompson
03a6679ba0 More btb cleanup. 2023-03-01 10:47:00 -06:00
Ross Thompson
554e7d0973 Minor fix to btb. 2023-03-01 10:45:40 -06:00
Ross Thompson
093d190c9a Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-03-01 10:04:13 -06:00
Ross Thompson
6880a052e0 Merge pull request #119 from eroom1966/main 
update ImperasDV testbench for memory privileges
 2023-03-01 09:50:00 -06:00
Ross Thompson
f141ec2777 Merge pull request #118 from davidharrishmc/dev 
Pulled to latest commit of riscv-arch-test
 2023-03-01 09:49:19 -06:00
eroom1966
f86a12f282 update testbench for memory privileges 
also update configuration to define value of mimpid
 2023-03-01 15:37:11 +00:00
Ross Thompson
a6917d07f3 Name cleanup. 2023-02-28 17:48:58 -06:00
David Harris
906e74dac2 Pulled to latest commit of riscv-arch-test 2023-02-28 15:03:59 -08:00
Kip Macsai-Goren
58ab6ec805 Merge remote-tracking branch 'upstream/main' into bit-manip 2023-02-28 14:41:51 -08:00
Kip Macsai-Goren
f63748f097 Merge remote-tracking branch 'origin' into bit-manip 2023-02-28 14:39:57 -08:00
Ross Thompson
4c0e7f297a Found the performance bug with the branch predictor btb power saving update. 2023-02-28 15:57:34 -06:00
Ross Thompson
2ebe600f54 Name changes to reflect diagrams. 2023-02-28 15:37:25 -06:00
Ross Thompson
be4823f7dd Undid the btb update as it reduces performance. 2023-02-28 15:21:56 -06:00
Kevin Kim
df0d75034b bitmanip decoder spits out regwrite, w64, and aluop signals [NEEDS DEBUG] 2023-02-28 12:09:35 -08:00
Kevin Kim
b61d881c1b added BRegWrite, BW64, BALUOp signals to bctrl and controller 
-TODO: Main decode in bmuctrl must assert these 3 signals
 2023-02-28 11:54:10 -08:00
Kevin Kim
692e406976 changed shifter source select signal name 2023-02-28 11:41:40 -08:00
Kevin Kim
1506d50c63 rename result back to ALUResult in ALU 2023-02-28 07:27:34 -08:00
Ross Thompson
9dd3379744 This icpred and btb changes are causing a performance issue. 2023-02-27 20:00:50 -06:00
Ross Thompson
544abe2819 Modified the BTB to save power by not updating when the prediction is unchanged. 2023-02-27 17:37:29 -06:00
Ross Thompson
bc5aecf948 Merge branch 'main' of https://github.com/openhwgroup/cvw 2023-02-27 09:48:03 -06:00