10 Commits

Author	SHA1	Message	Date
bbracker	63bfd79009	slightly smarter dtim HREADY	2021-03-13 06:55:34 -05:00
David Harris	fe4d288589	Initial untested implementation of AMO instructions	2021-03-11 00:11:31 -05:00
bbracker	62dd9e3075	first merge of ahb fix	2021-03-05 14:24:22 -05:00
Noah Boorstin	cfcd7d1518	busybear: make imperas tests work again	2021-03-04 22:44:49 +00:00
Noah Boorstin	b3247eadd2	busybear: more adapting to new memory system	2021-03-01 18:50:42 +00:00
Noah Boorstin	2769b147cb	busybear: add 2nd dtim for bootram	2021-02-28 16:08:54 +00:00
David Harris	cc42655789	More memory interface, ALU testgen	2021-02-15 10:10:50 -05:00
David Harris	33110ed636	Data memory bus integration	2021-02-07 23:21:55 -05:00
David Harris	9f9c3bcece	Changed DTIM latency to 2 cycles	2021-02-02 14:22:12 -05:00
David Harris	07af481b67	Reorganized src hierarchically	2021-01-30 11:50:37 -05:00