Ross Thompson
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f1049be6c1
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More cleanup and formatting.
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2023-01-20 12:09:21 -06:00 |
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Ross Thompson
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11c44006c4
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Integrated the missing zifence tests into the regression test.
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2023-01-20 10:34:49 -06:00 |
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Ross Thompson
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b2676e1dd4
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Somehow the imperas files spilled into the main branch.
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2023-01-17 15:39:34 -06:00 |
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Ross Thompson
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b26cec1ef4
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Possible optimization of gshare.
I don't believe the Writeback stage ghr is needed.
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2023-01-13 12:39:29 -06:00 |
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Ross Thompson
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f59e1d03fc
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Added instruction logger.
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2023-01-12 10:09:34 -06:00 |
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Ross Thompson
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e3df1d3326
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Restored to default configuration.
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2023-01-09 00:21:45 -06:00 |
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Ross Thompson
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f643b45b97
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Added branch outcome logger to testbench
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2023-01-07 13:16:57 -06:00 |
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Ross Thompson
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48cf8d58b4
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally
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2023-01-06 15:18:13 -06:00 |
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Ross Thompson
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81fe08192e
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Added python script to post process performance counter metrics.
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2023-01-06 15:15:54 -06:00 |
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Ross Thompson
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cd17d296d2
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Added code to print out performance counters at end of each test.
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2023-01-05 18:00:11 -06:00 |
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Ross Thompson
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942acb354e
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Closing in on icache flushed by FlushD rather than TrapM.
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2022-12-22 20:19:09 -06:00 |
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David Harris
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a5dc09c97f
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Added assertion about atomics needing caches
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2022-12-21 13:57:28 -08:00 |
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Ross Thompson
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a6ffb4cef3
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Added timeout check to testbench.
A watchdog checks the value of PCW. If it does not change within 1M cycles immediately stop simulation and report an error.
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2022-12-21 09:18:00 -06:00 |
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Ross Thompson
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7a352edf13
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Attempted to make a cache test.
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2022-12-18 17:15:08 -06:00 |
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Ross Thompson
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9d1cb9337e
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Updated tests for fpga and BP.
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2022-12-18 16:24:26 -06:00 |
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David Harris
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3bef12b108
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Renamed DIV_BITSPERCYCLE to IDIV_BITSPERCYCLE
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2022-12-15 08:23:34 -08:00 |
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Ross Thompson
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cedb234013
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Turns out the merge of dirty and tag bits is complicated by the need to have byte write enables rather than bit write enables. Putting on hold for now.
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2022-11-30 11:01:25 -06:00 |
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Ross Thompson
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0454eb95ad
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Preparing to merge dirty and tag srams.
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2022-11-30 10:40:48 -06:00 |
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Ross Thompson
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de538d1c2f
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Intermediate commit. Replaced flip flop dirty bit array with sram.
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2022-11-30 00:08:31 -06:00 |
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Ross Thompson
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ac864a6ca3
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Merged together bram1p1rw with sram1p1rw as sram1p1rw.
Fixed a major issue with the real SRAM implemenation.
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2022-09-21 12:20:00 -05:00 |
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Ross Thompson
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3571fb18c2
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Modified regression tests to add some ahb configurations.
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2022-09-07 12:03:58 -05:00 |
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David Harris
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03e731b3ff
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Set correct size of IROM/DTIM and allow FLEN>XLEN with DTIM
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2022-08-26 21:05:20 -07:00 |
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David Harris
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812158aeee
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Replaced DTIM and IROM with DTIM_SUPPORTED, IROM_SUPPORTED, and base and range for each
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2022-08-26 20:26:12 -07:00 |
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David Harris
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95dd50a567
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Renamed DMEM to DTIM and added checks about compatibility of DTIM/IROM and virtmem
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2022-08-26 20:12:03 -07:00 |
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Ross Thompson
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db635e3ad2
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-08-25 16:01:02 -05:00 |
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David Harris
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302a7fa294
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Extended HADDR to PA_BITS
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2022-08-25 13:11:36 -07:00 |
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Ross Thompson
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179aec3616
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Still not working with rv32ic.
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2022-08-25 15:03:54 -05:00 |
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Ross Thompson
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3b612d6201
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Possible fixes for earily messup of rv32ic and rv64ic configs.
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2022-08-25 14:42:08 -05:00 |
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Ross Thompson
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e605ef57dc
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BROKEN. Don't use this commit.
Issue running cacheless with bus.
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2022-08-25 11:02:46 -05:00 |
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Ross Thompson
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b0aea77b20
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Added generate around uncore.
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2022-08-25 10:35:24 -05:00 |
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Ross Thompson
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769af32f2a
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Renamed RAM to UNCORE_RAM.
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2022-08-24 18:09:07 -05:00 |
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Ross Thompson
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fc22e807e2
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Merged testbench-fpga into testbench.
Modified SDC to simplify LimitTimers. LimitTimers needs to be 0 for implmementation and 1 for simulation.
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2022-08-24 17:52:25 -05:00 |
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Ross Thompson
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4a371b6829
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added SD card and external ram to common testbench.
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2022-08-24 13:27:18 -05:00 |
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Ross Thompson
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51adf6cba9
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Modified the lsu/ifu memory configurations.
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2022-08-24 12:35:15 -05:00 |
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David Harris
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7fcc852687
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Q depends on D
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2022-08-23 08:29:59 -07:00 |
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David Harris
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e714b75888
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LSU minor edits
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2022-08-23 07:35:47 -07:00 |
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David Harris
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16a92eaf10
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Updated testbench assertions.
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2022-08-23 07:23:24 -07:00 |
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David Harris
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75a265159b
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Increased timeout threshold to avoid timeout building riscof tests on slow machine
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2022-07-27 04:05:21 +00:00 |
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David Harris
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9ecef0c4cd
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fixed testbench merge comflict
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2022-07-26 06:21:46 -07:00 |
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David Harris
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2d7f4b133c
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More work toward riscof tests
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2022-07-26 06:19:13 -07:00 |
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David Harris
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5c54c5b521
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Added rv32f tests to RV64gc
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2022-07-25 23:29:05 +00:00 |
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Ross Thompson
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8193946996
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-07-23 08:41:59 -05:00 |
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Daniel Torres
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95fdd408ee
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commiting current changes to riscof wally tests
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2022-07-22 11:14:04 -07:00 |
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Katherine Parry
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7268b4b334
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removed underflow from inexactct calculation
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2022-07-18 17:51:18 +00:00 |
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Ross Thompson
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0ef6137ab9
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Added degree of freedom to cache/sram. The sram width in bits is no longer defined by XLEN, but instead a separate parameter. This is decoupled from LINELEN, XLEN, and WORDLEN.
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2022-07-17 21:05:31 -05:00 |
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Ross Thompson
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8356e5d742
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Updated cache sram's to use 1 sram for all words in a way. Still needs to modified to support subdivision by max physical sram width.
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2022-07-17 16:20:04 -05:00 |
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Katherine Parry
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18d7fee541
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally
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2022-07-12 22:37:20 +00:00 |
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DTowersM
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fe7d03a3da
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added some preliminary support for coremark XLEN=32, made sure rv64 not impacted
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2022-07-11 21:13:09 +00:00 |
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Katherine Parry
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97e7e619d9
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moved fpu ieu write data mux to lsu
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2022-07-08 23:56:57 +00:00 |
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David Harris
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8be1dafbd6
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Removed testbench code that ignores mismatch on zero signatures
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2022-07-08 09:17:31 +00:00 |
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