David Harris
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711ed99b3b
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Merge pull request #67 from eroom1966/main
Add RVVI Address size to configure MMU operations
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2023-02-06 08:01:28 -08:00 |
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eroom1966
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ae3ac02556
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remove dead code for ignoring fflags/fcsr
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2023-02-06 15:53:29 +00:00 |
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eroom1966
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d88b56eebc
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remove leading space
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2023-02-06 14:01:05 +00:00 |
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eroom1966
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232bfbcfd0
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remerge changes
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2023-02-06 13:43:12 +00:00 |
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Kevin Kim
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a81a48007e
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zbb handles sign
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2023-02-05 16:50:13 +00:00 |
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Kevin Kim
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4c28c28644
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began sign/zero extend
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2023-02-05 16:37:32 +00:00 |
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David Harris
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69e9c85d7a
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Merge pull request #63 from davidharrishmc/dev
Cleanup
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2023-02-04 20:15:12 -08:00 |
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David Harris
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077edbf78d
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changed USE_SRAM to modify wally-config rather than wally-shared
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2023-02-04 20:13:24 -08:00 |
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David Harris
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7cf98811f3
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Parenthesized reduction operators to avoid DC lint
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2023-02-04 18:49:47 -08:00 |
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David Harris
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66fa1e67bb
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Removed redundant USE_SRAM from wally-shared.vh (already in wally-config.vh)
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2023-02-04 18:49:25 -08:00 |
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David Harris
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2303da01a8
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-02-04 18:32:31 -08:00 |
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David Harris
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4091418f00
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Merge pull request #64 from mmasserfrye/main
Now modifying dtim and irom even when USESRAM=1
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2023-02-04 18:11:39 -08:00 |
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Kevin Kim
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b871277435
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modularized byte instruction handling into byte.sv; passes lint
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2023-02-05 01:04:39 +00:00 |
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Kevin Kim
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8782f2d352
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modularized count into cnt.sv; passes lint
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2023-02-05 00:48:26 +00:00 |
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Kevin Kim
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0fa7798607
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zbb handles popcnt and passes lint
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2023-02-05 00:11:24 +00:00 |
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Kevin Kim
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4b6a757d68
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added population count in generic modules
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2023-02-05 00:11:12 +00:00 |
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Madeleine Masser-Frye
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9454eb921d
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Now modifying dtim and irom even when USESRAM=1
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2023-02-05 00:02:50 +00:00 |
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Kevin Kim
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8b6aad27c7
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Started count instructions
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2023-02-04 20:01:41 +00:00 |
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David Harris
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6abd5dd644
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-02-04 09:59:44 -08:00 |
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David Harris
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5256d3a625
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More progress on debug.S, but it crashes in Spike
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2023-02-04 09:59:22 -08:00 |
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Ross Thompson
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4fed1d5e3d
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Merge branch 'main' of https://github.com/openhwgroup/cvw
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2023-02-04 11:28:26 -06:00 |
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Ross Thompson
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d7a65b2576
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Updates to imperas test bench.
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2023-02-04 11:28:23 -06:00 |
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David Harris
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43668a3fc5
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Developing debug test
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2023-02-04 08:31:47 -08:00 |
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David Harris
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b09002c71d
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Fixed license on testbench files
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2023-02-04 08:19:20 -08:00 |
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David Harris
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2c69adc5f7
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Started making debug testcase
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2023-02-04 08:18:55 -08:00 |
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David Harris
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ae54860805
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Renamed wally-piplined.do to wally.do
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2023-02-04 04:38:41 -08:00 |
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David Harris
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835f793db9
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Merge pull request #62 from davidharrishmc/dev
../synthDC/Makefile
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2023-02-04 04:29:56 -08:00 |
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David Harris
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be08523ba0
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Added license headers
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2023-02-04 04:29:27 -08:00 |
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David Harris
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f89e642312
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../synthDC/Makefile
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2023-02-04 04:19:09 -08:00 |
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David Harris
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52e028fc7a
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Merge pull request #53 from davidharrishmc/dev
Removed pipelined hierarchy and renamed regression to sim
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2023-02-04 04:15:02 -08:00 |
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David Harris
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6b9ae4fc89
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Fixed merge issues on synthDC PR
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2023-02-04 04:13:40 -08:00 |
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David Harris
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e831baf335
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Improved illegal NaN-box detection and formatted fsgninj
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2023-02-04 03:42:20 -08:00 |
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David Harris
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18750e0f0a
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Merge pull request #61 from mmasserfrye/main
USE_SRAM parameter, makefile config cleaning
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2023-02-04 03:28:44 -08:00 |
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Madeleine Masser-Frye
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4be41ae25c
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finishing the job of the last commit
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2023-02-04 10:24:01 +00:00 |
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Madeleine Masser-Frye
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b78ce62748
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added use sram parameter, cleaned up config writing, added single synth functionality to wallySynth
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2023-02-04 09:50:36 +00:00 |
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David Harris
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fa276d67b4
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Merge pull request #60 from ross144/main
Optimized PCLink logic.
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2023-02-03 16:42:27 -08:00 |
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Ross Thompson
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f5468ebd7a
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Replaced PCLinkX registers with a +2/4 adder in the execution stage.
David and I estimate this is lower hardware cost.
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2023-02-03 18:19:47 -06:00 |
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Ross Thompson
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583d87afc7
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Change CurrPtr to Ptr in RAS.
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2023-02-03 17:40:20 -06:00 |
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Kevin Kim
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202c45bef2
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Merge branch 'main' of https://github.com/kipmacsaigoren/cvw
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2023-02-03 18:39:26 +00:00 |
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Kevin Kim
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9c3f062f4d
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arch32ba includes the 32i_m tests instead of 64
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2023-02-03 17:40:02 +00:00 |
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Kip Macsai-Goren
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fc549d1595
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Merge remote-tracking branch 'upstream/main' into main
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2023-02-03 09:31:06 -08:00 |
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David Harris
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34fbfeb5cd
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Removed redundant line from synthesis makefile
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2023-02-03 08:36:51 -08:00 |
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David Harris
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97ee3732fe
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Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
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2023-02-03 08:36:11 -08:00 |
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David Harris
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4dca69f205
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Updated division radix test script with paths, but script is out of date for files it manipulates
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2023-02-03 08:36:03 -08:00 |
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Kevin Kim
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3d67e48bef
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Merge branch 'main' of https://github.com/kipmacsaigoren/cvw
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2023-02-03 16:00:36 +00:00 |
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Kevin Kim
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d47a44a62f
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ALU changes (ZBB)
- handles inverted operand instructions
- handles shift-and-add instructions
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2023-02-03 16:00:32 +00:00 |
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David Harris
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1763de52ea
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Merge pull request #54 from ross144/main
Fixed issue #50, itlb and dcache flush interlock
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2023-02-03 06:30:30 -08:00 |
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Ross Thompson
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4547da80ea
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Fixed bug #49.
FFLAGS was updated while the pipeline was stalled.
Also I found serveral performance counters which had similar issues.
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2023-02-03 00:39:26 -06:00 |
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Ross Thompson
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659b511616
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Lee Moore found another bug using imperas.
An ITLB miss concurrent with a d cache flush did not interlock.
The LSU should suppress the d cache flush until the hptw fills the missing tlb entry.
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2023-02-02 23:52:21 -06:00 |
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Kevin Kim
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a0adcf6a85
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Merge branch 'openhwgroup:main' into main
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2023-02-02 21:41:55 -08:00 |
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