Github_Repos/cvw
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6,957 Commits 5 Branches 2 Tags 53 MiB
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73 Commits

Author SHA1 Message Date
David Harris
71f7d66dbf gitmodules 2022-01-31 00:59:44 +00:00
James Stine
8fd975da74 Remove book_flow to add back later - will add synthDC back within 30m 2022-01-28 08:18:30 -06:00
David Harris
064a02de18 Added synthesis submodules 2022-01-27 14:31:34 +00:00
David Harris
3a7786877a Removed and restored embench-iot 2022-01-25 22:12:28 +00:00
David Harris
12e08d8055 Fixed sumtest reference output; added embench benchmark directory 2022-01-24 23:21:09 +00:00
David Harris
55b4423329 Added E extension, and downloaded riscv-dv and embench-iot to addins 2022-01-17 14:42:59 +00:00
David Harris
486cfdc3a5 Added C test cases 2022-01-11 21:01:48 +00:00
David Harris
0e023e29d8 Code cleanup 2022-01-07 04:07:04 +00:00
Katherine Parry
b3ebce0365 some FPU test fixes 2022-01-06 23:03:20 +00:00
David Harris
81b382e51e Switched riscv-arch-test to current hash 2021-12-29 18:52:52 +00:00
David Harris
f9ab193ca8 Added partially working MMU tests 2021-12-29 03:14:16 +00:00
David Harris
48bb534658 Started FIR test code and started incorporating Imperas tests 2021-12-25 22:39:51 +00:00
David Harris
787af4287e Removed riscv-isa-sim submodule from Wally; use it in /opt/riscv instead 2021-12-21 02:35:41 +00:00
David Harris
d9f569afe1 Added irscv-arch-test and rsicv-isa-sim 2021-12-15 12:38:35 -08:00
Ross Thompson
af9f97454d Cleaned up fpga synthesis script. 2021-12-13 18:26:54 -06:00
David Harris
55f3979b67 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-13 07:57:49 -08:00
kwan
8f79a12cbb priviledge .* removed, passed regression 2021-12-13 00:34:43 -08:00
David Harris
d936342c97 Refactoring ALU and datapath muxes 2021-12-08 12:33:53 -08:00
Katherine Parry
80f026a734 FMA uses one LOA 2021-12-07 14:15:43 -08:00
kwan
05a838aee2 .* in ifu/ifu.sv eliminated 2021-12-02 09:45:55 -08:00
David Harris
42780ba40b Added coremark scripts to regression directory 2021-12-01 09:08:06 -08:00
Kevin Kim
cae3a44b9a added arch-test submodule 2021-11-30 18:22:08 -08:00
Kevin Kim
b5e86b2e20 Added git submodules 
-riscv-arch-test
-rscv-isa-sim
submodules are added in addins/ directory
 2021-11-30 18:16:37 -08:00