12 Commits

Author	SHA1	Message	Date
Domenico Ottolia	787ae978d7	Fix misa synthesis bug (for real now)	2021-04-22 15:35:20 -04:00
Domenico Ottolia	939e36a151	Fix misa bug	2021-04-22 00:59:07 -04:00
Domenico Ottolia	d5f86fadac	Add tests for sepc register	2021-04-20 23:50:53 -04:00
Domenico Ottolia	e02ff60b07	Fix synthesis warnings for privileged unit (replace 'initial' settings)	2021-04-20 17:57:56 -04:00
Domenico Ottolia	1bdfac6a77	Cause an Illegal Instruction Exception when attempting to write readonly CSRs	2021-04-08 05:12:54 -04:00
Thomas Fleming	f2604797fb	Add all PMP addr registers	2021-03-24 21:58:33 -04:00
Noah Boorstin	847bf0b9a6	change ifndef to generate/if	2021-03-18 12:50:19 -04:00
Noah Boorstin	0af002eb2f	busybear: make CSRs only weird for us	2021-03-05 00:46:32 +00:00
Noah Boorstin	c03f69fb80	Change CSR reset and available bits to conform to OVPsim ... Now actually keeping perfectly in line with OVP for the first 100k instrs. Yay.	2021-02-04 22:03:45 +00:00
David Harris	756352f129	Minor tweaks	2021-02-02 19:44:37 -05:00
David Harris	92bf1674b4	Moved fpu to temporary location to fix compile and cleaned up interface formatting	2021-02-01 23:44:41 -05:00
David Harris	07af481b67	Reorganized src hierarchically	2021-01-30 11:50:37 -05:00