11 Commits

Author	SHA1	Message	Date
Thomas Fleming	8c410b6fbe	Install dtlb in dmem	2021-03-04 03:30:06 -05:00
Thomas Fleming	1a2db17ee5	Install tlb into ifu	2021-03-04 03:11:34 -05:00
David Harris	0258901865	Cleaned out unused signals	2021-02-26 09:17:36 -05:00
David Harris	225102047a	Clean up bus interface code	2021-02-26 01:03:47 -05:00
David Harris	38b8cc652c	All tests passing with bus interface	2021-02-24 07:25:03 -05:00
David Harris	cc42655789	More memory interface, ALU testgen	2021-02-15 10:10:50 -05:00
David Harris	842c374de9	Debugging instruction fetch	2021-02-09 11:02:17 -05:00
David Harris	33110ed636	Data memory bus integration	2021-02-07 23:21:55 -05:00
David Harris	429f48e766	Rename ifu/dmem/ebu signals to match uarch diagram	2021-02-02 15:09:24 -05:00
David Harris	92bf1674b4	Moved fpu to temporary location to fix compile and cleaned up interface formatting	2021-02-01 23:44:41 -05:00
David Harris	07af481b67	Reorganized src hierarchically	2021-01-30 11:50:37 -05:00