Jordan Carlin
fb40f04772
Update rocky.yml
2024-10-14 00:43:00 -07:00
Jordan Carlin
9e9e301127
Update rocky.yml
2024-10-14 00:42:59 -07:00
Jordan Carlin
e9d1c501eb
Update rocky.yml
2024-10-14 00:42:59 -07:00
Jordan Carlin
81e3b50242
Update rocky.yml
2024-10-14 00:42:59 -07:00
Jordan Carlin
a111541da5
Update rocky.yml
2024-10-14 00:42:59 -07:00
Jordan Carlin
5717089c02
Create rocky.yml
2024-10-14 00:42:59 -07:00
Jordan Carlin
319982a65c
Update install.yml
2024-10-14 00:42:58 -07:00
Jordan Carlin
0029483139
Update install.yml
2024-10-14 00:42:58 -07:00
Jordan Carlin
9fe94b86d2
Update install.yml
2024-10-14 00:42:58 -07:00
Jordan Carlin
8dcdd71830
Update install.yml
2024-10-14 00:42:58 -07:00
Jordan Carlin
9a399e7ef0
Update install.yml
2024-10-14 00:42:58 -07:00
Jordan Carlin
ac5a469034
Update install.yml
2024-10-14 00:42:57 -07:00
Jordan Carlin
9f38600cac
Update install.yml
2024-10-14 00:42:57 -07:00
Jordan Carlin
780147dfd6
Update install.yml
2024-10-14 00:42:57 -07:00
Jordan Carlin
6406931958
Test installation regression GitHub action
2024-10-14 00:42:57 -07:00
Jordan Carlin
b8d50fd621
Switch back to standard riscv-arch-test repo
2024-10-14 00:42:47 -07:00
Jordan Carlin
dc98f29ffa
Add --no-buildroot option to installation script
2024-10-14 00:06:05 -07:00
Jordan Carlin
77eb250ef6
Fix sphinx version format
2024-10-14 00:05:37 -07:00
Jordan Carlin
48ee8b0a18
Fix sphinx version format
2024-10-14 00:02:07 -07:00
Jordan Carlin
0cb1ac70f6
Limit Sphinx version
2024-10-14 00:01:47 -07:00
Jordan Carlin
e7b9369f7f
Merge pull request #1008 from davidharrishmc/dev
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Fix mcountinhibit bit 1 that should be hardwired to 0
2024-10-13 22:44:35 -07:00
David Harris
61a5aeaa03
Merge pull request #1004 from rosethompson/ignorerequest
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Modified the LSU and HPTW to reduce the complexity of the IgnoreRequestTLB logic
2024-10-13 21:56:14 -07:00
David Harris
5f5dac2bda
Some Imperas configuration changes to match unimplemented Wally registers
2024-10-13 21:42:16 -07:00
David Harris
669ee6ca12
WALLY-init-lib improvements to support functional coverage
2024-10-13 20:59:41 -07:00
David Harris
9ef211b40d
mcountinhibit bit 1 should be hardwired to 0. Discovered during functional coverage testing
2024-10-13 20:59:01 -07:00
Jordan Carlin
1cb22fbe8a
Fix duplicate riscv-isac
2024-10-13 20:35:36 -07:00
Jordan Carlin
ab1797753b
Revert "Use python 3.11 for rhel 8"
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This reverts commit d76cda4dd7613583d41a4bc4624a1915f490a583.
2024-10-13 20:28:51 -07:00
Jordan Carlin
1076b9c179
Use python 3.11 for rhel 8
2024-10-13 20:28:43 -07:00
Jordan Carlin
20b157de62
Remove manual riscv-isac installation
2024-10-13 20:28:35 -07:00
Jordan Carlin
5f28ee5959
Test forked riscv-arch-test
2024-10-13 20:28:25 -07:00
Jordan Carlin
826b3775b6
Add setuptools to pip
2024-10-13 20:28:09 -07:00
Jordan Carlin
5580bf2fb0
Attempt clone and install riscv-isac
2024-10-13 20:27:56 -07:00
Jordan Carlin
8f3d888da5
Attempt to install riscof only
2024-10-13 20:27:46 -07:00
Jordan Carlin
3c88bb9771
Temporarily remove sphinx-rtd-theme from requirements.txt
2024-10-13 20:27:36 -07:00
Jordan Carlin
0f2dae0da1
Temporarily remove sphinx from requirements.txt
2024-10-13 20:27:24 -07:00
Jordan Carlin
3084fa9c37
Temporarily remove PyYAML from requirements.txt
2024-10-13 20:27:13 -07:00
Jordan Carlin
1e34a97068
Temporarily remove matplotlib
2024-10-13 20:26:57 -07:00
David Harris
1655c6f67c
Merge pull request #1006 from Mysterio-Abdullah/Config
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Configuring Zcb
2024-10-13 17:45:24 -07:00
Mysterio-Abdullah
da35944dce
Configuring Zcb
2024-10-13 17:41:59 -07:00
David Harris
515af445b5
Merge pull request #1005 from jordancarlin/mem_limit
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Limit number of threads if 8 GB of memory
2024-10-13 17:34:55 -07:00
Jordan Carlin
d5649f6f1d
Limit number of threads if 8 GB of memory
2024-10-13 17:32:38 -07:00
Rose Thompson
2ef7005ea6
Fixed name of test and added to tests.vh
2024-10-13 15:29:27 -05:00
David Harris
21e6ccd8dd
Waived tlbMisaligned lockstep sim due to Issue 976 and improved timeout warning message
2024-10-12 16:39:17 -07:00
Rose Thompson
5011084d40
Revert "This is a better solution. It's closer to the original book HPTW FSM,"
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This actually adds to the critical path and it's more complex than I feel comfortable.
This reverts commit 1ded4a972f
2024-10-11 17:02:51 -05:00
Rose Thompson
1ded4a972f
This is a better solution. It's closer to the original book HPTW FSM,
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but is slightly more complex in RTL. Instead it looks at ReadDataM
for the PTE for PBMT faults. I was worried this would cause critical
path issues but I think it is ok. ReadDataM is used only to created
PBMT and this directly controlls the enable to a flop and the state
inputs to the FSM.
2024-10-11 16:47:18 -05:00
Rose Thompson
4c7eb1d11f
Renamed IgnoreRequestTLB to HPTWFlushW and IgnoreRequest to LSUFlushW.
2024-10-11 15:41:40 -05:00
Rose Thompson
37d3db916b
Resolved the HPTW's not taking the PBMT fault on the right cycle by
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having the fsm branch to fault on any cycle a HPTWFaultM occurs. This
of course changes the figure in the book but it really relevant to
PBMT. This appeared to work because the HPTW happened to also generate
an access fault at the end of the walk and the logic produced both
faults. I wrote new test which confirms just the one is generated.
2024-10-11 15:31:20 -05:00
Rose Thompson
7a92d41ef5
Simplified logic around IgnoreRequest and HPTWFaultM.
2024-10-11 14:41:52 -05:00
Rose Thompson
fe5f342d2f
Does not work. But there is a bug hiding the IgnoreRequest confusion.
2024-10-11 12:07:26 -05:00
Rose Thompson
6a905aa2f2
Possible start to resolution on issue #839 .
2024-10-10 17:14:27 -05:00
