David Harris
|
77fb1b57f4
|
Fix Issue 145
|
2023-03-22 04:33:14 -07:00 |
|
David Harris
|
376bbcc71d
|
Renamed intdivrestoring to div
|
2023-03-21 05:51:02 -07:00 |
|
David Harris
|
0fd385e5de
|
Renamed intdivrestoring to div
|
2023-03-20 16:22:06 -07:00 |
|
David Harris
|
0ecde4ab4f
|
formatting cleanup
|
2023-03-20 12:45:10 -07:00 |
|
David Harris
|
471305bda0
|
Eliminate transitions to FLUSH and WRITEBACK in cachefsm for READ_ONLY_CACHE
|
2023-03-19 10:41:47 -07:00 |
|
David Harris
|
835381a122
|
Removed flq from LLEN=64
|
2023-03-19 10:25:04 -07:00 |
|
David Harris
|
02e7e7d011
|
Added comments about PMP checker fixes when test cases will be ready to initialize PMP before entering user mode
|
2023-03-19 05:46:34 -07:00 |
|
David Harris
|
031cc6967a
|
Fix Issue #120 about SIE/SIP being 0 unless MIDELEG bits are set. However, this fix breaks the wally32/64priv tests in regression.
|
2023-03-18 10:10:58 -07:00 |
|
David Harris
|
70e4c71f41
|
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
|
2023-03-18 09:24:37 -07:00 |
|
David Harris
|
08ce265420
|
Replaced FenceM with InvalidateICacheM for event counting of fence.i
|
2023-03-18 09:24:31 -07:00 |
|
Ross Thompson
|
407b3c488d
|
Book updates.
|
2023-03-14 13:09:50 -05:00 |
|
Ross Thompson
|
a27051b8a8
|
Updated NextAdr to NextSet.
|
2023-03-13 14:54:13 -05:00 |
|
Ross Thompson
|
cb019f9aed
|
Updated CAdr to CacheSet.
|
2023-03-13 14:53:00 -05:00 |
|
Ross Thompson
|
ede9d49ce4
|
Changes BTA to BPBTA.
|
2023-03-12 14:36:46 -05:00 |
|
Ross Thompson
|
e233b63752
|
Replaced DCACHE parameter with READ_ONLY_CACHE as the name was confusing in chapter 10.
|
2023-03-12 13:21:22 -05:00 |
|
David Harris
|
ed22433916
|
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
|
2023-03-10 12:47:30 -08:00 |
|
David Harris
|
2614448218
|
Simplified SLT and SLTU code in ALU
|
2023-03-09 15:14:52 -08:00 |
|
Ross Thompson
|
fa8a550e12
|
Merge branch 'main' of https://github.com/openhwgroup/cvw
|
2023-03-09 13:29:38 -06:00 |
|
Ross Thompson
|
6d2d7d181e
|
Updated testbench to record coremark performance counters.
Added comment about mtval probably not being correct for compressed instructions.
|
2023-03-08 17:11:27 -06:00 |
|
David Harris
|
ec0873ff16
|
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
|
2023-03-07 14:49:23 -08:00 |
|
kipmacsaigoren
|
01f78835cb
|
Merge branch 'openhwgroup:main' into priv-tests
|
2023-03-07 13:46:55 -08:00 |
|
David Harris
|
dce6d33531
|
editorconfig to specify tabs/spaces. Fixed some tabs. Turn off coverage to speed up simulation
|
2023-03-07 06:31:40 -08:00 |
|
Ross Thompson
|
17f80285ca
|
Merge branch 'main' of https://github.com/openhwgroup/cvw
|
2023-03-06 22:29:27 -06:00 |
|
Ross Thompson
|
b8dca927f2
|
Merge branch 'main' of https://github.com/openhwgroup/cvw
|
2023-03-06 18:39:15 -06:00 |
|
Ross Thompson
|
4b539de184
|
Renamed signals to be consistent with textbook.
|
2023-03-06 18:29:31 -06:00 |
|
Ross Thompson
|
6fc157e628
|
Renamed PCFSpill to PCSpillF.
|
2023-03-06 17:50:57 -06:00 |
|
Ross Thompson
|
e831efddaf
|
Renamed InstrFirstHalf to InstrFirstHalfF.
|
2023-03-06 17:48:57 -06:00 |
|
Ross Thompson
|
82ada79b11
|
Renamed ebuarbfsm to ebufsmarb to match figures.
|
2023-03-06 17:47:55 -06:00 |
|
David Harris
|
4fd461e520
|
Fixed bug about rv64 shifts only using 6 bits of funct7
|
2023-03-06 13:10:51 -08:00 |
|
David Harris
|
94dd39795e
|
Simplified decoder default to illegal instruction
|
2023-03-06 11:21:11 -08:00 |
|
David Harris
|
08f1ed8e53
|
More detailed decoding of load/store/branch/jump
|
2023-03-06 11:15:48 -08:00 |
|
David Harris
|
a01e0bd318
|
Improved decoding illegal instructions in controller
|
2023-03-06 11:02:42 -08:00 |
|
Kip Macsai-Goren
|
0ba1a59a70
|
added reset values to stime and stimecmp registers
|
2023-03-04 15:06:15 -08:00 |
|
Ross Thompson
|
dea5aae01e
|
Merge pull request #126 from davidharrishmc/dev
ImperasDV setup
|
2023-03-03 18:01:32 -06:00 |
|
David Harris
|
39c871ee0c
|
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
|
2023-03-03 15:54:42 -08:00 |
|
Ross Thompson
|
7dd8fa16c1
|
Renamed BTB misprediction to BTA.
|
2023-03-03 00:18:34 -06:00 |
|
Ross Thompson
|
bdab2c8506
|
Added divide cycle counter.
|
2023-03-02 23:59:52 -06:00 |
|
Ross Thompson
|
4b501f6e03
|
Added the i and d cache cycle counters.
|
2023-03-02 23:54:56 -06:00 |
|
Ross Thompson
|
b19d51b6a2
|
Added fence counter.
|
2023-03-02 23:29:20 -06:00 |
|
Ross Thompson
|
3dbfa96aef
|
Added csr write counter, sfence vma counter, interrupt counter, and exception counter.
|
2023-03-02 23:21:29 -06:00 |
|
Ross Thompson
|
cf4d8e6bd0
|
Added store stall to performance counters.
|
2023-03-02 23:10:54 -06:00 |
|
Ross Thompson
|
e257ec96ac
|
Reordered performance counters and added space for new ones.
|
2023-03-02 23:04:31 -06:00 |
|
David Harris
|
d51d93a3a8
|
Refactored Floating point division special case detection to avoid spurious trigger on Y for sqrt)
|
2023-03-02 20:00:47 -08:00 |
|
Ross Thompson
|
3d1ffac7d7
|
Cleaned up branch predictor performance counters.
|
2023-03-01 17:05:42 -06:00 |
|
David Harris
|
c761fb1054
|
Merge branch 'main' of https://github.com/openhwgroup/cvw into dev
|
2023-03-01 11:18:05 -08:00 |
|
David Harris
|
e78591093e
|
Renamed I/D TLBMissOrDAFault to TLBMissOrUpdateDA for consistency with UpdateDA
|
2023-03-01 11:18:00 -08:00 |
|
Ross Thompson
|
a61f8bc4cf
|
Set bp to use instruction class prediction by default.
|
2023-03-01 11:52:42 -06:00 |
|
Ross Thompson
|
e8744684cd
|
Branch predictor cleanup.
I think Ch 10 is now done except for BTB performance analysis and the section on running benchmarks and collecting data.
|
2023-03-01 11:24:24 -06:00 |
|
Ross Thompson
|
08a1153ae9
|
More btb cleanup.
|
2023-03-01 10:47:00 -06:00 |
|
Ross Thompson
|
dd2433f7ff
|
Minor fix to btb.
|
2023-03-01 10:45:40 -06:00 |
|