Ross Thompson
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d09b381183
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Fixed the amo on dcache miss cpu stall issue.
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2021-09-17 22:15:03 -05:00 |
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Ross Thompson
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b92070a67a
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Updated Dcache to fully support flush. This appears to work.
Updated PCNextF so it points to the correct PC after icache invalidate.
Build root crashes with PCW mismatch and invalid register writes.
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2021-09-17 10:25:21 -05:00 |
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Ross Thompson
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d4398c23fb
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Added states and all control and data path logic to support d cache flush. This is currently untested; however the existing regresss test passes.
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2021-09-16 18:32:29 -05:00 |
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Ross Thompson
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4ca0c0ea7d
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Added flush controls to cachway.
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2021-09-16 16:56:48 -05:00 |
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Ross Thompson
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3ff8d0095d
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Fixed dcache to prevent latches in FPGA synthesized design.
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2021-09-11 12:03:48 -05:00 |
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Ross Thompson
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939ff663a5
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Forgot to include a few files in the last few commits.
Also reorganized the dcache by read cpu path, write cpu path, and bus interface path.
Changed i/o names on subwordread to match signals in dcache.
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2021-08-25 22:30:05 -05:00 |
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