354 Commits

Author	SHA1	Message	Date
Ross Thompson	2294cbc1c6	Possible fix for trap concurent with xret. Fixes the priority so trap has higher priority than either sret or mret. Previous code had priority to xret in the trap logic and privilege logic, but not the csrsr logic. This caused partial execution of the instruction.	2022-04-07 16:56:28 -05:00
Katherine Parry	c307cff503	fixed errors and warnings in rv32e	2022-04-07 17:21:20 +00:00
Ross Thompson	9517fe9faf	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-04-05 15:42:07 -05:00
Ross Thompson	7abde2b566	Increazed fpga clock speed to 35Mhz. ... linux boot is much faster.	2022-04-05 15:09:49 -05:00
Katherine Parry	20885f4dea	generating all testfloat vectors	2022-04-04 17:17:12 +00:00
Ross Thompson	0ed34b8e63	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-04-04 10:56:10 -05:00
Ross Thompson	64846c800e	Constraint changes for 40Mhz wally.	2022-04-04 10:50:48 -05:00
Ross Thompson	0806d1a134	Updated the bootloader to use the flash card divider. This will allow wally to run at a faster speed than flash.	2022-04-04 10:38:37 -05:00
Ross Thompson	d83db2cde5	Fixed the SDC clock divider so it actually can work during reset. This will enable the fpga to operate at a faster clock while the SDC is < 10Mhz.	2022-04-04 09:57:26 -05:00
Ross Thompson	fd9a33e453	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-04-03 17:56:55 -05:00
David Harris	6966554ee8	Fixed bug with CSRRS/CSRRC for MIP/SIP	2022-04-03 20:18:25 +00:00
Ross Thompson	d135866098	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-04-02 16:39:54 -05:00
Ross Thompson	5ef6cde52e	Added more ILA signals.	2022-04-02 16:39:45 -05:00
Ross Thompson	f58a1eff9e	Fixed linting issues.	2022-04-01 15:20:45 -05:00
Ross Thompson	178ecaa451	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-04-01 12:50:34 -05:00
Ross Thompson	0340c0fd44	Added wave config ... added new signals to ILA.	2022-04-01 12:44:14 -05:00
bbracker	36c30b14c1	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-03-31 17:54:43 -07:00
bbracker	e60139d3ee	fix lingering overrun error bug	2022-03-31 17:54:32 -07:00
Ross Thompson	cb945a6a6a	Added PLIC to ILA.	2022-03-31 16:44:49 -05:00
Ross Thompson	1586f893b1	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-03-31 16:30:55 -05:00
Ross Thompson	7e05935348	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-03-31 15:50:04 -05:00
Ross Thompson	e81f317764	Notes on what to change in ram.sv.	2022-03-31 15:48:15 -05:00
bbracker	d32e1147bf	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-03-31 13:46:32 -07:00
bbracker	34c94f150e	simplify plic logic	2022-03-31 13:46:24 -07:00
David Harris	2ed1c9f14f	Added SystemVerilog flag to fma.do so that fma16 compiles properly	2022-03-31 17:00:38 +00:00
Ross Thompson	fb0eec0f76	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-03-31 11:39:41 -05:00
Ross Thompson	0942429b7f	Forced to go back to hard coded preload.	2022-03-31 11:39:37 -05:00
Ross Thompson	a6d090a7c0	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-03-31 11:38:55 -05:00
Ross Thompson	dc48d84dd6	Modified clint to support all byte write sizes.	2022-03-31 11:31:52 -05:00
David Harris	93d6b2fb62	Added synthesis script for fma16	2022-03-31 00:51:33 +00:00
David Harris	f917ed7ed0	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-03-30 23:06:36 +00:00
bbracker	54b9745a75	big interrupts refactor	2022-03-30 13:22:41 -07:00
Ross Thompson	b2a77da96b	Changed sram1p1rw to have the same type of bytewrite enables as bram.	2022-03-30 11:38:25 -05:00
David Harris	44f94173bf	Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main	2022-03-30 16:26:27 +00:00
Ross Thompson	3ac736e2d5	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-03-30 11:09:44 -05:00
Ross Thompson	370a075fa1	Partial cleanup of memories.	2022-03-30 11:09:21 -05:00
Ross Thompson	1993069986	Converted over to the blockram/sram memories. Now I just need to cleanup. But before the cleanup I wan to make sure the FPGA synthesizes with these changes and actually keeps the preload.	2022-03-30 11:04:15 -05:00
Ross Thompson	fc2b4453ec	rv32gc and rv64gc now use the updated ram3.sv (will rename to ram.sv) which uses a vivado block ram compatible memory. Still need to update simpleram.sv to use this block ram compatible memory.	2022-03-29 23:48:19 -05:00
Ross Thompson	de2672231d	Partial fix to allow byte write enables with fpga and still get a preload to work.	2022-03-29 19:12:29 -05:00
David Harris	057ee56d7e	Updated synthesis to look at fma16.v, other scripts to use fma16.v instead of fma16.sv	2022-03-29 19:16:41 +00:00
David Harris	049c55769a	fpu compare simplification, minor cleanup	2022-03-29 17:11:28 +00:00
Kip Macsai-Goren	ad106e7130	made machine timer bit of IP registers unwriteable so it can only change when the interrupt actually changes	2022-03-29 02:26:42 +00:00
bbracker	46ffa4b079	fix typo that Madeleine found	2022-03-28 15:39:29 -07:00
Kip Macsai-Goren	dc9635b757	fixed double multiplication on vectored interrupts	2022-03-28 19:12:31 +00:00
Ross Thompson	7099259ff7	I think this version of csri matches what is required in the spec. ExtIntS should not be written into the SEIP register bit.	2022-03-25 13:10:31 -05:00
Ross Thompson	7a824eaae1	Found a way to remove a bus input into MMU. PAdr can be made into VAdr by selecting the faulting virtual address when writing the DTLB.	2022-03-24 23:47:28 -05:00
bbracker	150a7b234b	tabs vs spaces disagreement	2022-03-24 17:11:41 -07:00
bbracker	9f60256f22	1st attempt at multiple channel PLIC	2022-03-24 17:08:10 -07:00
Ross Thompson	58668812c1	Moved WriteDataM register into LSU.	2022-03-23 14:17:59 -05:00
Ross Thompson	07b7dbc922	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-03-23 14:10:38 -05:00