11 Commits

Author	SHA1	Message	Date
Rose Thompson	7223b15134	Merge branch 'rvvi'	2024-07-22 12:01:01 -05:00
Ross Thompson	2d8973df1d	Updated wavefile to use new names.	2024-06-19 13:57:28 -07:00
Ross Thompson	64712d2243	Updated wave to match changes in testbench.	2024-06-19 13:51:50 -07:00
Rose Thompson	dc09e1c0c5	Modified names so they don't conflict with FPGA's axi signals.	2024-05-24 16:38:47 -05:00
Rose Thompson	1f7d732dca	Moved the rvvisynth code to testbench since I only want this for simulation and fpga.	2024-05-24 16:10:58 -05:00
Rose Thompson	bf9f45d319	We have a simulation of the ethernet transmission working. ... This commit does not include the source files for the ethernet as it does not belong to cvw. I'll want to fork that repo and make it a submodule as I need to change the source a bit.	2024-05-24 11:25:42 -05:00
Rose Thompson	b127c19242	Merge branch 'main' into rvvi	2024-05-20 16:31:06 -05:00
Rose Thompson	93ea5b0c1e	Fixed wavefile to have function logger.	2024-05-10 08:50:42 -05:00
slmnemo	554f818a8c	Fixed wave.do to match new conditional generate block names	2024-04-16 14:43:38 -07:00
Rose Thompson	d0d1166e3f	Got the separation of the -G and +variable arguments in the questa do file. ... regression still runs.	2024-04-06 18:04:48 -05:00
David Harris	a1d3e5b15e	Moved do files into questa	2024-04-05 18:42:48 -07:00