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Author SHA1 Message Date
Ross Thompson
9adcf86a40 Modified the icache memory to read using the virtual (non physical) address in the PCNextF stage. 
This allows recovering from an ITLBMiss to be 1 cycle after and simplifies the hptw slightly.
 2021-12-19 14:57:42 -06:00
Ross Thompson
0257c08641 Renamed MemAdrM to IEUAdrM. This will free the name MemAdrm for use in the DCache. 2021-12-19 14:00:30 -06:00
Ross Thompson
620f4a58d4 Adds FSM to LSU which will handle the interactions between the hptw and dcache. This will dramatically simplify the dcache by removing all walker states. 2021-12-19 13:55:57 -06:00
Ross Thompson
fdf493bd47 minro change. comments about needed changes in dcache. 2021-12-19 13:53:02 -06:00
David Harris
c04c56dae1 Renamed zero to eq in flag generation 2021-12-19 11:49:15 -08:00
David Harris
e5d2d7a3fd Controller fix 2021-12-18 22:08:23 -08:00
David Harris
8a597390e0 Renamed RD1D to R1D, etc. 2021-12-18 21:26:00 -08:00
David Harris
7fb4213751 Simplified shifter right input 2021-12-18 10:25:40 -08:00
Ross Thompson
f601b3ae53 Merge branch 'tlb_fixes' into main 2021-12-18 12:24:17 -06:00
David Harris
d97d34ee32 Simplified Shifter Right input 2021-12-18 10:21:17 -08:00
David Harris
852c521328 Shared ALU mux input for shifts 2021-12-18 10:08:52 -08:00
David Harris
a7d7f852a6 Factored out common parts of shifter 2021-12-18 10:01:12 -08:00
David Harris
7868c0da55 Cleaning shifter 2021-12-18 09:43:09 -08:00
David Harris
b453454b24 Moved W64 truncation after result mux 2021-12-18 09:27:25 -08:00
David Harris
2a5a7eff82 Forwarding logic factoring 2021-12-18 05:40:38 -08:00
David Harris
1212e21eba Simplified FWriteInt interfaces by merging into RegWrite 2021-12-18 05:36:32 -08:00
David Harris
da1df17fbb Do File cleanups 2021-12-17 17:45:26 -08:00
Ross Thompson
2f86e84843 Merge remote-tracking branch 'origin/tlb_fixes' into main 2021-12-17 14:40:29 -06:00
Ross Thompson
79ec4161b6 Added more debugging code for FPGA. 2021-12-17 14:40:25 -06:00
Ross Thompson
5264577dcf Possible fix for icache deadlock interaction with hptw. 2021-12-17 14:38:25 -06:00
David Harris
7a8162497b Added irscv-arch-test and rsicv-isa-sim 2021-12-15 12:38:35 -08:00
David Harris
3a9071e509 Renamed MemAdrE to IEUAdrE and moved the MemAdrM flop from IEU to LSU to reduce wires crossing hierarchies 2021-12-15 12:10:45 -08:00
David Harris
f0059b7b3a IEU cleanup: 2021-12-15 11:38:26 -08:00
Ross Thompson
9f798250ea Oups missed files in the last commit. 2021-12-15 10:25:08 -06:00
Ross Thompson
54767822ec Reverted 23Mhz to 10Mhz. The flash card can't work at that speed. 
added icache debugging signals.
 2021-12-15 10:24:29 -06:00
David Harris
f4957fdac1 Renamed dtim->ram and boottim ->bootrom 2021-12-14 13:43:06 -08:00
David Harris
6b27e19381 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-14 13:05:47 -08:00
David Harris
b42faa794a changed ideal memory to MEM_DTIM and MEM_ITIM 2021-12-14 13:05:32 -08:00
Ross Thompson
45b38ea9fe Comments for dcache and icache refactoring. 2021-12-14 14:46:29 -06:00
David Harris
ee5c2e6101 renamed rv32/64g to rv32/64gc in configuration 2021-12-14 11:22:00 -08:00
David Harris
eb33021f40 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-14 11:15:58 -08:00
David Harris
dd0d4c0add ALU and datapath cleanup 2021-12-14 11:15:47 -08:00
Ross Thompson
5e4e44a2cc Added patch file for the qemu modifications. 
Added instructions for building and installing qemu.
 2021-12-13 18:36:00 -06:00
Ross Thompson
b224fbb447 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-13 18:30:14 -06:00
Ross Thompson
0e9e561726 Updated .gitignore file to hide fpga outputs. 2021-12-13 18:30:10 -06:00
Ross Thompson
f061a26411 Cleaned up fpga synthesis script. 2021-12-13 18:26:54 -06:00
Ross Thompson
8c55bd7b7e Possible fix for icache and ptw interlock deadlock issue. 2021-12-13 18:23:43 -06:00
Ross Thompson
b9c8b808ea Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-13 17:16:20 -06:00
Ross Thompson
7d00649b61 Formating changes to cache fsms. 2021-12-13 17:16:13 -06:00
Ross Thompson
5361f69639 Fixed some typos in the dcache ptw interaction documentation. 2021-12-13 15:47:20 -06:00
David Harris
74cf0eb96a Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-13 07:57:49 -08:00
David Harris
1ca949c0bb Simplified ALU and source multiplexers pass tests 2021-12-13 07:57:38 -08:00
kwan
5ede8126fd priviledge .* removed, passed regression 2021-12-13 00:34:43 -08:00
kwan
b05bc3c19e test 2021-12-13 00:31:51 -08:00
kwan
83dae9d774 priviledge .* fixed, passed local regression 2021-12-13 00:22:01 -08:00
Kevin
3aad1137c2 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-12-12 17:53:41 -08:00
Kevin
b928d01bb8 dot stars conversions on the rest of the testbenches 2021-12-12 17:53:26 -08:00
Ross Thompson
8e39034dbd Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-12-12 17:33:29 -06:00
Ross Thompson
2f282e5570 Revert "Privilige .*s removed" 
This reverts commit 471f267987.
 2021-12-12 17:31:57 -06:00
Ross Thompson
fdbb7b6ef3 Revert "Priviledged .* removed" 
This reverts commit 96ac298596.
 2021-12-12 17:31:39 -06:00