Ross Thompson
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2e60edaedd
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Added new device trees for vcu118 and vcu108 boards.
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2022-10-24 17:45:10 -05:00 |
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Ross Thompson
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d68bdfbade
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Updated the device tree to use 30Mhz instead of 10Mhz for the cpu timebase.
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2022-10-20 15:05:39 -05:00 |
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slmnemo
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e3a7e3e2f3
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changes suggested by ben, hopefully fixing buildroot (which is now not running)
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2022-05-20 18:42:38 -07:00 |
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bbracker
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6f63b88c60
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upgrade Buildroot Makefile to also copy over vmlinux
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2022-04-25 07:36:59 -07:00 |
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bbracker
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cd70175e5a
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less hardcoded paths in Makefile
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2022-04-21 20:42:02 -07:00 |
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David Harris
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1e19cf9f14
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Simplified profile for UART boot; added warnings on UART Rx errors
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2022-04-21 04:54:45 +00:00 |
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bbracker
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20c82b6f1a
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parsePlicState.py bugfix
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2022-04-13 13:04:43 -07:00 |
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bbracker
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3465d8cd32
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improve testbench-linux.sv to correctly load in PLIC IntEnable checkpoint and to handle edge case where interrupt is caused by enabling interrupts in SSTATUS
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2022-04-13 03:37:53 -07:00 |
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bbracker
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0d4ec9b3f9
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fix bugs in PLIC checkpoint state parsing
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2022-04-13 01:59:21 -07:00 |
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bbracker
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1bb5e1f35b
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whoops fix address for PLIC int enables in checkpoint generation
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2022-04-13 01:36:09 -07:00 |
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bbracker
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54c5f7f607
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deprecate remove_dup.awk in favor of expanding parseGDBtoTrace.py to internally remove duplicates; this way the instruction counts in traps.txt are hopefully now in sync with the line numbers of all.txt
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2022-04-07 19:43:22 -07:00 |
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bbracker
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008089b470
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-07 08:37:44 -07:00 |
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bbracker
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0a0956fad0
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fix parseQEMUtoGDB.py to pass on interrupt messages correctly
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2022-04-07 04:47:15 -07:00 |
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kaveh Pezeshki
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49aae4b2e9
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using -S for busybox objdump to provide source code snippets
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2022-04-06 23:06:49 +00:00 |
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bbracker
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0f394ba18b
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-04-06 07:50:57 -07:00 |
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bbracker
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0a8ce0593a
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filter traps list down to just interrupts
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2022-04-06 07:49:44 -07:00 |
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bbracker
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ea0471dcc7
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change RAM size in genInitMem.sh
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2022-04-06 07:49:04 -07:00 |
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David Harris
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23da303ad3
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Added bootmem source ccode
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2022-04-05 23:22:53 +00:00 |
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David Harris
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c6960ede37
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Changed Linux disassembly to -S to preserve source code lines
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2022-04-01 16:49:13 +00:00 |
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bbracker
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a5c32898a0
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checkpointSweep is bash-specific, so add shebang to make it so
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2022-03-28 13:40:50 -07:00 |
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bbracker
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501dc7cd68
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fix genCheckpoint.sh binary memory dump
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2022-03-27 20:54:59 -07:00 |
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bbracker
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9b5bbd29b4
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change genCheckpoint.sh to only log 128MB of RAM
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2022-03-27 19:16:39 -07:00 |
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bbracker
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4e1b50e50c
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fix parseGDBtoTrace.py to expect the CSRs that QEMU actually prints out
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2022-03-27 19:05:44 -07:00 |
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bbracker
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800bc85519
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refactored buildroot configuration
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2022-03-27 15:13:03 -07:00 |
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bbracker
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0eeb6cc5b5
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-27 15:11:42 -07:00 |
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bbracker
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8d5c231a13
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change devicetree to expect only 128MB of RAM
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2022-03-27 15:11:36 -07:00 |
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bbracker
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6f6663cd67
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fix multiple-context PLIC checkpoint generation
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2022-03-25 01:02:22 +00:00 |
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bbracker
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4b376e2834
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1st attempt at multiple channel PLIC
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2022-03-24 17:08:10 -07:00 |
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Ross Thompson
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4ca9458534
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added SIP, SIE, and SSTATUS to checkpoints. Can't seem to get the linux testbench to force SIP.
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2022-03-22 21:28:34 -05:00 |
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bbracker
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099fc34c10
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change genTrace to dump UART output to file so we can see how far parsing got
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2022-03-08 09:52:17 -08:00 |
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bbracker
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742e8d98cd
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fix up PLIC and UART checkpointing
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2022-03-07 23:48:47 -08:00 |
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bbracker
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bfaf496473
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change UART state saving to temporarily modify LCR so that DLAB=0 when reading addresses 0 and 1 so that we get RBR and IER instead of divisor latch registers
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2022-03-07 22:12:08 -08:00 |
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bbracker
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097301635a
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change checkpoint generation to integrate GDB scripting more cleanly and save UART and PLIC state
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2022-03-07 17:59:49 -08:00 |
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bbracker
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409dd48706
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modify debug.sh to not rely on external GDB script
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2022-03-07 11:56:04 -08:00 |
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bbracker
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4bf95714eb
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add debug.sh
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2022-03-07 19:52:19 +00:00 |
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bbracker
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483aad2a05
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update checkpointSweep in accordance to having removed trace parsing feature
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2022-03-06 14:55:51 -08:00 |
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bbracker
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bea2faeda6
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remove vestigial silencePipe mechanism
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2022-03-06 14:54:35 -08:00 |
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bbracker
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11e9bbf3e4
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needed to initialize checkpoint directory
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2022-03-06 14:51:25 -08:00 |
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bbracker
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d007208aa9
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no longer use cythonization on python parser scripts because its a little complicated and has marginal benefit
|
2022-03-06 14:40:26 -08:00 |
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bbracker
|
f64b7776ed
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give genCheckpoint the same de-sudo'ing treatement
|
2022-03-06 14:37:12 -08:00 |
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bbracker
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7182ec228f
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better to use $tvDir variable rather than abs path
|
2022-03-06 14:33:53 -08:00 |
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bbracker
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8f2e67984f
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replace sudo's with suggestions in genRecording.sh
|
2022-03-06 14:31:55 -08:00 |
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bbracker
|
e57b5208dc
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replace sudo's in genTrace.sh with suggested commands
|
2022-03-06 14:24:50 -08:00 |
|
bbracker
|
91f327e109
|
small bugfix to suggested sudo commands for linux testvectors
|
2022-03-06 14:16:23 -08:00 |
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bbracker
|
742b9d884d
|
remove checkpoint trace generation since that requires qemu hacking and because we are able to generate the whole trace on VLSI
|
2022-03-06 14:04:30 -08:00 |
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bbracker
|
e3f735cc1a
|
recommend sudo commands without automatically executing them in genInitMem.sh
|
2022-03-06 13:30:19 -08:00 |
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bbracker
|
efee8d3a22
|
change from clang to gcc when compiling testvector-generation executables
|
2022-03-06 13:18:53 -08:00 |
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bbracker
|
1fc7856c36
|
add extractFunctionRadix step to buildroot Makefile
|
2022-03-05 19:02:07 -08:00 |
|
bbracker
|
4eb46785fc
|
change genInitMem.sh to check for sufficient directory privileges rather than invoke sudo
|
2022-03-05 18:04:00 -08:00 |
|
bbracker
|
1bb73dad7d
|
change main.config so that buildroot expects linux.config and busybox.config to be at $RISCV/buildroot
|
2022-03-02 17:46:33 +00:00 |
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