Harshini Srinath
70b6d01d2e
Update amoalu.sv
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Program clean up
2023-06-12 12:54:50 -07:00
Harshini Srinath
a53cdbd166
Update spill.sv
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Program clean up
2023-06-12 12:50:11 -07:00
Harshini Srinath
7fa3b87275
Update irom.sv
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Program clean up
2023-06-12 12:44:09 -07:00
Harshini Srinath
128e88a7a0
Update ifu.sv
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Program clean up
2023-06-12 12:38:52 -07:00
Harshini Srinath
e2a9e257c7
Update decompress.sv
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Program clean up
2023-06-12 12:27:55 -07:00
Harshini Srinath
a849fa78cb
Update CodeAligner.py
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Program clean up
2023-06-12 12:25:47 -07:00
Harshini Srinath
80289a1b67
Update shifter.sv
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Program clean up
2023-06-12 12:23:45 -07:00
Harshini Srinath
201d61c575
Update regfile.sv
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Program clean up
2023-06-12 12:21:25 -07:00
Harshini Srinath
055e41bc42
Update ieu.sv
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Program clean up
2023-06-12 12:19:04 -07:00
Harshini Srinath
f5a77be56f
Update extend.sv
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Program clean up
2023-06-12 12:15:33 -07:00
Harshini Srinath
1a59222a08
Update datapath.sv
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Program clean up
2023-06-12 12:13:58 -07:00
Harshini Srinath
ea0199b3a6
Update prioritythermometer.sv
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Program clean up
2023-06-11 19:18:21 -07:00
Harshini Srinath
8951f965fb
Update or_rows.sv
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Program clean up
2023-06-11 19:16:37 -07:00
Harshini Srinath
aec1330986
Update neg.sv
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Program clean up
2023-06-11 19:15:28 -07:00
Harshini Srinath
0a08da2daf
Update counter.sv
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Program clean up
2023-06-11 19:12:57 -07:00
Harshini Srinath
6c76ca1fef
Update adder.sv
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Program clean up
2023-06-11 19:09:18 -07:00
Harshini Srinath
420ee8dad9
Update unpackinput.sv
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Program clean up
2023-06-11 17:09:11 -07:00
Harshini Srinath
7e0dedea19
Update fctrl.sv
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Program clean up
2023-06-11 17:03:29 -07:00
Harshini Srinath
3bc164a4ca
Update fcmp.sv
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Program clean up
2023-06-11 16:54:52 -07:00
Harshini Srinath
74fa15bcb4
Update fsgninj.sv
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Program clean up
2023-06-11 16:52:00 -07:00
Harshini Srinath
2739ea26a7
Update fregfile.sv
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Program clean up
2023-06-11 16:49:20 -07:00
Harshini Srinath
7770f7e79b
Update fpu.sv
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Program clean up
2023-06-11 16:43:31 -07:00
Harshini Srinath
ca170c8b81
Update fhazard.sv
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Program clean up
2023-06-11 16:06:44 -07:00
Harshini Srinath
d9b58c44cf
Update fcvt.sv
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Program clean up
2023-06-11 16:05:14 -07:00
Harshini Srinath
21015c8e4a
Update fcvt.sv
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Program clean up
2023-06-11 15:59:20 -07:00
Harshini Srinath
fb1e5e401f
Update fctrl.sv
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Program clean up
2023-06-10 19:38:50 -07:00
Harshini Srinath
71248a7523
Update fcmp.sv
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Program clean up
2023-06-10 19:35:58 -07:00
Harshini Srinath
db2ac9604a
Update fcmp.sv
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Program clean up
2023-06-10 19:34:58 -07:00
Harshini Srinath
02e8689999
Update fclassify.sv
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Program clean up
2023-06-10 19:30:18 -07:00
Harshini Srinath
61ebfdb55f
Update controllerinput.sv
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Program clean up
2023-06-10 18:26:06 -07:00
Harshini Srinath
a90bbba617
Update ahbinterface.sv
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Program clean up
2023-06-10 18:18:16 -07:00
Harshini Srinath
2f47a6e04f
Program clean up
2023-06-10 18:13:40 -07:00
Harshini Srinath
107ebf6a3c
Update ebu.sv
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Code clean up
2023-06-09 08:53:27 -07:00
Harshini Srinath
b4e5f43acb
Update subcachelineread.sv
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Code clean up
2023-06-09 08:50:51 -07:00
Harshini Srinath
7475a0eeed
Update cacheway.sv
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Code clean up
2023-06-09 08:48:11 -07:00
Harshini Srinath
fcac659e34
Update cacheLRU.sv
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Code clean up
2023-06-09 08:43:38 -07:00
Harshini Srinath
1f1fcce062
Update cache.sv
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Formatting clean up
2023-06-09 08:39:57 -07:00
Ross Thompson
9bae203d1c
Updated parameterization types. Modelsim version 2022.1 did requires defaults to a 32 bit integer. The base and ranges for the address decoder need to be larger.
2023-06-09 09:28:24 -05:00
David Harris
62a8332c8f
Merge pull request #313 from ross144/main
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Fix extraneous force in testbench which keep btb in reset.
2023-06-06 08:41:34 -07:00
David Harris
df212ce7d8
Merge pull request #312 from ross144/main
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Fixed typo in coremark makefile.
2023-06-06 05:44:22 -07:00
Ross Thompson
822e60bd3d
Found the coremark performance issue. The testbench was continuously forcing the BTB to all zeros. Once fixed it resolved the performance problem.
2023-06-05 15:42:05 -05:00
James Stine
51d77b0414
Update some spacing to make it look better
2023-06-05 11:03:06 -05:00
Ross Thompson
e56497101a
Updated source code to be compatible with verilator 5.011 for lint only.
2023-05-31 10:44:23 -05:00
Ross Thompson
ab91fe7436
Cleanup parameterization for verilator 5.010.
2023-05-31 10:02:34 -05:00
Ross Thompson
3c94c186db
Possible fix for Linux bug and bug 203. ImperasDV mismatches in linux boot around 571M instructions after the login prompt.
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This bug occurs when there are back to back HPTW requests and the first generates an access fault during the walk. The old implementation uses a delayed version of the fault to prevent the HTPW fsm from transitioning out of the IDLE state. Because the first request generates the fault and the second request is pipelined the second request appears as if it also faults so the FSM does not perform the walk.
The new implementation adds a FAULT state. When the HPTW generates an access fault it transitions to this state removes the HPTWStall and then transitions to IDLE. There may still be a remaining bug here if the pipeline is stalled for another reason. However I don't think it is possible by construction. The only possible sources of stalls at this point would be IFU and LSU stalls and both are required to make this condition happen.
2023-05-30 15:20:24 -05:00
Ross Thompson
903f2f9063
Merge branch 'param-lim-merge'
2023-05-26 16:25:35 -05:00
Ross Thompson
b8474b208e
Uncore is now parameterized.
2023-05-26 16:24:12 -05:00
Ross Thompson
340aac0934
Got the branch predictor parameterized using Lim's method. Also had to add a global enum included in both cvw.sv and the configs which defines the branch predictor types. This should be synthesizable, but I'll need to double check.
2023-05-26 16:00:14 -05:00
Ross Thompson
e6d25b7f70
Finished fpu parameterization using Lim's method.
2023-05-26 14:40:06 -05:00
Ross Thompson
ef2bb7df93
fdiv is now parameterized using Lim's method.
2023-05-26 14:25:14 -05:00
