Ross Thompson
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c2b0e61466
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Removed WalkerInstrPageFault from icache, privilege unit, lsu, and hptw.
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2021-12-28 12:33:07 -06:00 |
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David Harris
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0c57b61ace
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2021-12-20 21:09:20 -08:00 |
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David Harris
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001c39d8eb
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Fixing paths in wally-setup.sh
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2021-12-20 21:08:34 -08:00 |
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Ross Thompson
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53736096a6
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-12-20 10:03:19 -06:00 |
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David Harris
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193885c958
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Moved generate of conditional units to hart
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2021-12-19 17:03:57 -08:00 |
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David Harris
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1196e5c191
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Moved generate statements for optional units into wallypipelinedhart
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2021-12-19 16:53:41 -08:00 |
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Ross Thompson
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0257c08641
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Renamed MemAdrM to IEUAdrM. This will free the name MemAdrm for use in the DCache.
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2021-12-19 14:00:30 -06:00 |
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Ross Thompson
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79ec4161b6
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Added more debugging code for FPGA.
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2021-12-17 14:40:25 -06:00 |
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kwan
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5ede8126fd
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priviledge .* removed, passed regression
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2021-12-13 00:34:43 -08:00 |
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kwan
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b05bc3c19e
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test
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2021-12-13 00:31:51 -08:00 |
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kwan
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83dae9d774
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priviledge .* fixed, passed local regression
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2021-12-13 00:22:01 -08:00 |
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kwan
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96ac298596
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Priviledged .* removed
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2021-12-12 09:55:45 -08:00 |
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kwan
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471f267987
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Privilige .*s removed
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2021-12-12 09:54:14 -08:00 |
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David Harris
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708b914a65
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Lint cleanup from wallypipeliendhart
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2021-10-23 10:29:52 -07:00 |
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Ross Thompson
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bb3e94d68a
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Modified the preformance counter's InstRet to include ECALL and EBREAK by changing the hazard logic so these instructions don't self flush the W stage.
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2021-08-23 15:46:17 -05:00 |
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Kip Macsai-Goren
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bb8ec549a7
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fixed issue with tlbflush remaining high during a stalled sfence instruction
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2021-07-21 17:43:36 -04:00 |
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Ross Thompson
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ae2371f2ce
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Added performance counters for dcache access and dcache miss.
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2021-07-19 22:12:20 -05:00 |
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David Harris
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49ec45d04d
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hptw: Removed NonBusTrapM from LSU
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2021-07-17 15:22:24 -04:00 |
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Ross Thompson
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4549a9f1c9
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Merge branch 'main' into dcache
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2021-07-15 11:55:20 -05:00 |
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Ross Thompson
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e17de4eb11
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Separated interruptM into PendingInterruptM and InterruptM. The d cache now takes in both exceptions and PendingInterrupts.
This solves the committedM issue.
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2021-07-14 15:00:33 -05:00 |
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Katherine Parry
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b9edbb15eb
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Fixed writting MStatus FS bits
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2021-07-13 13:22:04 -04:00 |
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Katherine Parry
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acdd2e4504
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Fixed writting MStatus FS bits
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2021-07-13 13:20:30 -04:00 |
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David Harris
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68d1f87101
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Fixed InstrValid from W to M stage for CSR performance counters
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2021-07-13 13:19:13 -04:00 |
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Ross Thompson
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d85bf23af3
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Merged several of the load/store/instruction access faults inside the mmu.
Still need to figure out what is wrong with the generation of load page fault when dtlb hit.
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2021-07-06 13:43:53 -05:00 |
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David Harris
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6785ed9994
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Implemented TSR, TW, TVM, MXR status bits
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2021-07-06 01:32:05 -04:00 |
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David Harris
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a5c0dc8c81
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Fixed MPRV and MXR checks in TLB
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2021-07-04 13:20:29 -04:00 |
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David Harris
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b5df9b282d
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Added support for PMP lock bits in csrm and repartitioned design to pass around 8-bit PMPCFG entries
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2021-07-04 11:39:59 -04:00 |
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David Harris
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648c09e5ef
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Optimized PMP checker logic and added support for configurable number of PMP registers
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2021-07-02 11:04:13 -04:00 |
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bbracker
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ced5039776
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Revert "fixed forwarding"
This reverts commit 0f4a4a6ade.
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2021-06-24 17:39:37 -04:00 |
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bbracker
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0f4a4a6ade
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fixed forwarding
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2021-06-24 11:20:21 -04:00 |
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David Harris
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aef408af58
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Reversed [0:...] with [...:0] in bus widths across the project
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2021-06-21 01:17:08 -04:00 |
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David Harris
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e03912f64c
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Cleaned up name of MTIME register in CSRC
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2021-06-18 07:53:49 -04:00 |
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bbracker
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7d1469a06c
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provide time and timeh CSRs based on CLINT's counter
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2021-06-17 08:38:30 -04:00 |
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bbracker
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7a652139b5
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mcause test fixes and s-mode interrupt bugfix
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2021-06-16 17:37:08 -04:00 |
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David Harris
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79ee817d91
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Reverted MIDELEG and MEDELEG to XLEN so busybear passes
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2021-06-10 23:47:32 -04:00 |
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David Harris
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9dd3857c26
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Fixed lint WIDTH errors
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2021-06-09 20:58:20 -04:00 |
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David Harris
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9a17556de4
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Start to parameterize number of PMP Entries
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2021-06-08 15:29:22 -04:00 |
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bbracker
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17960a6484
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Ah big ole merge! Passes sim-wally-batch and linting, so should be fine
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2021-06-08 12:41:25 -04:00 |
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bbracker
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5026a42fac
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* GPIO comprehensive testing
* MEPC more aware if M stage has actually committed
* UART interrupt testing progress
* UART added read IIR side effect of lowering THRE intr
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2021-06-08 12:32:46 -04:00 |
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David Harris
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1e67db2f0c
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Second attept to commit refactoring config files
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2021-06-07 12:37:46 -04:00 |
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Kip Macsai-Goren
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d69501c4fa
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Cleaned up some unused signals
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2021-06-04 21:04:19 -04:00 |
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Kip Macsai-Goren
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b99b5f8e0e
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moved privilege dfinitions into wally-constants, upgraded relevant includes
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2021-06-04 17:55:07 -04:00 |
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Kip Macsai-Goren
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7e41b17e65
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restructured so that pma/pmp are a part of mmu
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2021-06-04 17:05:07 -04:00 |
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David Harris
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b836679ae1
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Started MMU
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2021-06-04 11:59:14 -04:00 |
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bbracker
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28abd28b1f
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fixed InstrValid signals and implemented less costly MEPC loading
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2021-06-02 10:03:19 -04:00 |
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bbracker
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a45b61ede9
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turns out I should not have tried renaming FStallD to FPUStallD because that name was already used! All the same it does feel weird to have two such signals floating around \(ah pun!\)
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2021-05-28 23:11:37 -04:00 |
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Katherine Parry
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409438bc95
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floating point infinite loop removed from imperas tests
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2021-05-18 10:42:51 -04:00 |
|
Thomas Fleming
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86a93d77b4
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Implement PMP checker and revise PMA checker
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2021-05-03 17:37:42 -04:00 |
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Thomas Fleming
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94d734cca9
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
Conflicts:
wally-pipelined/src/ebu/ahblite.sv
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2021-05-03 14:02:19 -04:00 |
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Katherine Parry
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9252d08b41
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fpu imperas tests run
|
2021-05-01 02:18:01 +00:00 |
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