13 Commits

Author	SHA1	Message	Date
David Harris	2b241f8bbd	Set bit width of DMEM/IROM_SUPPORTED and fixed address decoding	2022-08-26 21:18:18 -07:00
David Harris	f0b4f69b65	Added IROM and DTIM decoding to adrdecs	2022-08-26 20:45:43 -07:00
David Harris	812158aeee	Replaced DTIM and IROM with DTIM_SUPPORTED, IROM_SUPPORTED, and base and range for each	2022-08-26 20:26:12 -07:00
David Harris	95dd50a567	Renamed DMEM to DTIM and added checks about compatibility of DTIM/IROM and virtmem	2022-08-26 20:12:03 -07:00
Ross Thompson	e605ef57dc	BROKEN. Don't use this commit. ... Issue running cacheless with bus.	2022-08-25 11:02:46 -05:00
Ross Thompson	769af32f2a	Renamed RAM to UNCORE_RAM.	2022-08-24 18:09:07 -05:00
Ross Thompson	51adf6cba9	Modified the lsu/ifu memory configurations.	2022-08-24 12:35:15 -05:00
Ross Thompson	69d520a7eb	Removed replay from the config files.	2022-07-24 00:34:11 -05:00
slmnemo	528869ef14	Removed references to initialization files	2022-06-23 16:50:27 -07:00
DTowersM	4e5d7ec3d6	changed DCACHE_LINELENINBITS and ICACHE_LINELENINBITS to 512, had to modigy the wfi test to increase timee before interupt to mantain compatability	2022-06-10 00:37:53 +00:00
David Harris	8066ba45e8	Preliminary support for big endian modes. Regression passes but no big endian tests written yet.	2022-05-08 06:46:35 +00:00
Kip Macsai-Goren	3d1e1202f3	set WFI timeout to after 16 bits of counting for all configs	2022-04-28 18:14:08 +00:00
Kip Macsai-Goren	da29193f9b	removed atomic, floating point from privileged tests configs	2022-04-25 19:13:15 +00:00