5 Commits

Author	SHA1	Message	Date
Ross Thompson	8e51935082	Converted branch predictor preloads to use system verilog rather than modelsim's load command.	2021-03-15 12:39:44 -05:00
Thomas Fleming	e57b6cf18c	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main ... Conflicts: wally-pipelined/src/ebu/ahblite.sv	2021-03-11 00:15:58 -05:00
Ross Thompson	9a93193d6a	Oups. I forgot to update other do files with the commands to preload the branch predictor memories.	2021-03-05 15:23:53 -06:00
Thomas Fleming	85dcbee86b	Place tlb parameters into constant header file	2021-03-05 13:35:24 -05:00
Brett Mathis	11e2666bb2	Parallel FSR's and F CTRL logic	2021-02-04 02:25:55 -06:00