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105 Commits

Author SHA1 Message Date
Ross Thompson
7c8d2e9b78 Partially working icache. 
The current issue is a StallF is required to halt the icache from getting an updated PCF. However
if the dmemory is the reason for a stall it is possible for the icache stall to hold the d memory request continuously causing d memory to repeatedly read from memory.  This keeps StallF high and
the icache FSM is never allowed to complete.
 2021-04-22 10:20:36 -05:00
Thomas Fleming
88bd151d55 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 
Conflicts:
	wally-pipelined/src/ifu/ifu.sv
 2021-04-21 20:01:08 -04:00
Thomas Fleming
70c801331a Implement virtual memory protection 2021-04-21 19:58:36 -04:00
Teo Ene
008b308b79 Fixed most relevant remaining synthesis compilation warnings with Ben 2021-04-21 16:06:27 -05:00
Ross Thompson
649589ee2c Broken icache. Design is done. Time to debug. 2021-04-20 19:55:49 -05:00
Jarred Allen
59b340dac9 Merge branch 'main' into cache 2021-04-19 00:05:23 -04:00
Thomas Fleming
2c4682c4be Connect tlb and icache properly 2021-04-15 14:48:39 -04:00
Jarred Allen
357aed75ee A few more cache fixes 2021-04-13 01:07:40 -04:00
Jarred Allen
6ce4d44ae1 Merge from branch 'main' 2021-04-08 17:19:34 -04:00
Thomas Fleming
e807f5d771 Implement support for superpages 2021-04-08 02:44:59 -04:00
Ross Thompson
d901cfc848 Merge branch 'icache_bp_bug' into tests 
Not sure this merge is right.
 2021-04-06 21:46:40 -05:00
Thomas Fleming
f9bf2fbc01 Implement sfence.vma and fix tlb writing 2021-04-01 15:55:05 -04:00
Ross Thompson
f1107c5d7b Corrected a number of bugs in the branch predictor. 
Added performance counters to individually track
branches; jumps, jump register, jal, and jalr; return.
jump and jump register are special cases of jal and jalr.
Similarlly return is a special case of jalr.
Also added counters to track if the branch direction was wrong,
btb target wrong, or the ras target was wrong.
Finally added one more counter to track if the BP incorrectly predicts
a non-cfi instruction.
 2021-03-31 11:54:02 -05:00
Ross Thompson
1e83810450 Merge of main with the new icache and the branch predictor. I believe there is a bug in the icache with unaligned memory access. The second part of the access is incorrectly relying on the PCF being the address of the next two bytes of the instruction. However this is not always the case as the branch predictor can get the wrong target address. The icache needs to generate the +2 address internally. 2021-03-30 23:18:20 -05:00
Thomas Fleming
e3d548d452 Merge remote-tracking branch 'origin/main' into main 
Bring icache and MMU code together

Conflicts:
	wally-pipelined/src/ifu/ifu.sv
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 22:24:47 -04:00
Thomas Fleming
4b2765f8e2 Complete basic page table walker 2021-03-30 22:19:27 -04:00
ushakya22
ba01d57767 Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-30 15:25:07 -04:00
Ross Thompson
a3925505bf fixed some bugs with the RAS. 2021-03-30 13:57:40 -05:00
Jarred Allen
6cda818f09 Merge branch 'cache2' into cache 
Conflicts:
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 13:32:33 -04:00
Jarred Allen
85164c7a87 Merge branch 'main' into cache 
Conflicts:
	wally-pipelined/regression/wave-dos/ahb-waves.do
	wally-pipelined/src/ifu/ifu.sv
	wally-pipelined/testbench/testbench-busybear.sv
	wally-pipelined/testbench/testbench-imperas.sv
 2021-03-30 12:55:01 -04:00
ShreyaSanghai
da4086db79 Removed PCW and InstrW from ifu 2021-03-26 01:53:19 +05:30
Jarred Allen
e8e4e1bee2 rv64i linear control flow now working 2021-03-25 13:02:26 -04:00
bbracker
5327dcfcc8 instrfaults not respecting stalls bugfix 2021-03-25 00:16:26 -04:00
Jarred Allen
1f01a12be9 Merge branch 'main' into cache 2021-03-23 23:35:36 -04:00
Ross Thompson
dee5d16850 fixed a whole bunch of bugs with the branch predictor. Still an issue with how PCNextF is not updated because the CPU is stalled. 2021-03-23 16:53:48 -05:00
Shreya Sanghai
09b90557f7 PC counts branch instructions 2021-03-23 14:25:51 -04:00
Jarred Allen
99fa8beef3 Update icache interface 2021-03-22 15:04:46 -04:00
Jarred Allen
50c961bbe4 Merge changes from main 2021-03-18 18:58:10 -04:00
Shreya Sanghai
f35d3b39c8 removed unnecesary PC registers in ifu 2021-03-18 16:31:21 -04:00
Thomas Fleming
062c4d40da Connect tlb, pagetablewalker, and memory 2021-03-18 14:35:46 -04:00
Jarred Allen
5b174adc2a Fix BEQZ tests 2021-03-14 15:42:27 -04:00
Jarred Allen
003242ae8a Merge upstream changes 2021-03-14 14:57:53 -04:00
Ross Thompson
ccaaa829ce Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main 2021-03-12 14:58:04 -06:00
Ross Thompson
0637874cac Cleanup of the branch predictor flush and stall controls. 2021-03-12 14:57:53 -06:00
Jarred Allen
c0ee17b6ac Merge upstream changes 2021-03-09 21:20:34 -05:00
Thomas Fleming
97e9baa316 Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main 2021-03-05 13:35:44 -05:00
Thomas Fleming
e48dc38869 Export SATP_REGW from csrs to MMU modules 2021-03-05 01:22:53 -05:00
Jarred Allen
5da98b5381 Partial progress towards compressed instructions 2021-03-04 18:30:26 -05:00
Jarred Allen
b0f4d8e8d4 Remove rd2, working for non-compressed 2021-03-04 16:46:43 -05:00
Ross Thompson
619bbd9d83 Merge branch 'bp' into main 
Concerns:
1. I don't think the correct data buses are going to the multiplier.
2. I'm not sure the FlushF signal is correct.
 2021-03-04 13:35:46 -06:00
Ross Thompson
d0223da2f7 Converted to using the BTB to predict the instruction class. 2021-03-04 09:23:35 -06:00
Thomas Fleming
8c410b6fbe Install dtlb in dmem 2021-03-04 03:30:06 -05:00
Thomas Fleming
1a2db17ee5 Install tlb into ifu 2021-03-04 03:11:34 -05:00
Ross Thompson
6191fcb1af Shreya and I found a bug with the exeuction of JAL and JALR instructions. The link was only set in the writeback stage. Once the branch predictor started correctly predicting JAL(R)s the ALU and forwarding logic need to have the PCLinkE at the execution stage in case an instruction in the next two clocks need the data. 2021-02-26 20:12:27 -06:00
David Harris
0258901865 Cleaned out unused signals 2021-02-26 09:17:36 -05:00
David Harris
225102047a Clean up bus interface code 2021-02-26 01:03:47 -05:00
David Harris
38b8cc652c All tests passing with bus interface 2021-02-24 07:25:03 -05:00
Ross Thompson
597dd1e7e6 Added FlushF to hazard unit. 
Fixed some typos with the names of signals in the branch predictor.  They were causing signals to be not set.  Note there is a modelsim flag which prevents it from compiling if a logic is undefined.
I will look this up and add it to the compiler.
 2021-02-19 16:36:51 -06:00
Ross Thompson
bbe0db3ebe Integrated the branch predictor into the hardward. Not yet working. 2021-02-17 22:19:17 -06:00
David Harris
cc42655789 More memory interface, ALU testgen 2021-02-15 10:10:50 -05:00
David Harris
842c374de9 Debugging instruction fetch 2021-02-09 11:02:17 -05:00
David Harris
33110ed636 Data memory bus integration 2021-02-07 23:21:55 -05:00
David Harris
429f48e766 Rename ifu/dmem/ebu signals to match uarch diagram 2021-02-02 15:09:24 -05:00
David Harris
92bf1674b4 Moved fpu to temporary location to fix compile and cleaned up interface formatting 2021-02-01 23:44:41 -05:00
David Harris
07af481b67 Reorganized src hierarchically 2021-01-30 11:50:37 -05:00