Ross Thompson
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3b8bdc7b2d
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Created separate memory interface for the ddr4 fpga memory from the soc internal memory dtim.
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2021-11-17 12:47:19 -06:00 |
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Ross Thompson
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232d4a554f
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Have program which checks for sdc init and issues read, but read done is
not correctly being read back by the software. The error is in how the
sdc indicates busy.
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2021-09-24 15:53:38 -05:00 |
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Ross Thompson
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4256ef82b1
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SDC to ABHLite interface partially done.
Added SDC to adrdec and uncore.
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2021-09-24 10:45:09 -05:00 |
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David Harris
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3cb9e5acd3
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Fixed adrdecs to use Access signals for TIMs
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2021-07-05 23:42:58 -04:00 |
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David Harris
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c897bef8cd
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Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang.
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2021-07-04 01:19:38 -04:00 |
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Kip Macsai-Goren
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389b9a510e
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Removed AHB address, etc signals from physical memory checkers, replaced with physical address from cpu or ptw. Passes lint but not simulations.
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2021-06-24 19:59:29 -04:00 |
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David Harris
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1972d83002
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Refactored pmachecker to have adrdecs used in uncore
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2021-06-23 01:41:00 -04:00 |
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