slmnemo
3b4c14e048
Removed .* from muldiv.
2021-11-17 10:39:18 -08:00
Ross Thompson
11a21899d5
Fixed uart by reversing the bit order on transmit.
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Set prescale to 0.
2021-11-17 10:32:41 -06:00
Skylar Litz
e35faa9b8a
fixed interrupt timing bug
2021-11-16 16:46:17 -08:00
davidharrishmc
984a7a6ccd
Update README.md
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updated linux_testvectors path
2021-11-16 12:33:47 -08:00
David Harris
5a521e28ee
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-11-16 12:30:55 -08:00
bbracker
23bd24323b
get current privilege level from GDB for checkpoints
2021-11-15 14:49:00 -08:00
Ross Thompson
4af7a27d87
Have linux booting. Not sure about uart, but uart is now part of the ILA and I can see TX changing.
2021-11-12 17:37:07 -06:00
Ross Thompson
b8572d6a2a
Changed several things.
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Removed the need to use async flip flops in SDC.
Added arrs, a synchronizer for reset.
I think this works with the real FPGA hardware.
The last build did not include this arrs but it worked.
2021-11-12 11:13:50 -06:00
Skylar Litz
99a15e7897
fix timing of delayed interrupt
2021-11-11 09:35:51 -08:00
David Harris
f96152fa31
bringing Coremark back to life
2021-11-10 12:43:31 -08:00
kipmacsaigoren
e90d0eee72
fixed small errors causing overwrites in timing reports
2021-11-10 13:01:09 -06:00
Kevin Kim
a7684f1b59
Makefile added in regression directory:
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-cd's into imperas then runs make commands, finally running the tvLinker script
2021-11-09 10:55:48 -08:00
bbracker
24c5796680
genCheckpoint path bugfix
2021-11-06 15:25:10 -07:00
bbracker
b3288beb38
update README.md to reflect new tvLinker location
2021-11-06 15:02:16 -07:00
bbracker
1597e0dac6
increase expectations for buildroot and timeout count
2021-11-06 14:57:29 -07:00
bbracker
e585a173e5
automated checkpoint generator
2021-11-06 14:37:49 -07:00
bbracker
d0ad8d3ae3
update tvLinker to new shared dir
2021-11-06 14:15:16 -07:00
bbracker
31d38286da
make genCheckpoint accept instr count as argument
2021-11-06 14:14:15 -07:00
bbracker
24d3244cfe
checkpoint MIDELEG support
2021-11-06 03:44:23 -07:00
bbracker
1d3d7cbe1e
fix merge conflict
2021-11-05 23:42:15 -07:00
bbracker
3077769cbd
checkpoints now use binary ram files
2021-11-05 22:37:05 -07:00
kipmacsaigoren
e7b25f7c95
changed number of critical paths reported to 1, added lots of internal signals and new report files.
2021-11-05 11:59:33 -05:00
davidharrishmc
f540bb13c0
fixed 64i
2021-11-03 13:49:07 -07:00
davidharrishmc
099c4e8b6b
fixed 64i
2021-11-03 13:40:23 -07:00
davidharrishmc
d957d86f3b
added wally-riscv-arch-test compile commands
2021-11-03 13:30:21 -07:00
Kevin
b34569c358
changed code aligner to run recursively on a root directory
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-only runs the aligner on .sv files
-runs recursively on sub-directories
2021-11-03 10:49:34 -07:00
slmnemo
5fc12d4ae9
edited to include missing instructions
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added cd tests before cd imperas-riscv-tests to reflect new tests folder
modified cd ../addins so we can point to it from the new imperas-riscv-tests within the tests folder
added instructions so the buildroot test exists
2021-11-03 01:50:00 -07:00
slmnemo
ec214e4bf0
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-11-03 00:50:27 -07:00
bbracker
e4cf044932
fix testbench interrupt timing
2021-11-02 21:19:12 -07:00
bbracker
730c52da23
genCheckpoint syntax fix
2021-11-01 15:31:38 -07:00
bbracker
8563c0f016
linux testgen refactor
2021-11-01 14:09:49 -07:00
David Harris
db268471b6
added some missing files
2021-11-01 13:36:07 -07:00
David Harris
0c829dd62c
simplified header and footer
2021-11-01 13:24:18 -07:00
David Harris
910957704b
Add3d wally32i test
2021-11-01 13:17:49 -07:00
David Harris
4b57af9cff
PIPELINE test running
2021-11-01 12:44:35 -07:00
David Harris
c306884e2c
Adding custom Wally test infrastructure
2021-11-01 08:48:46 -07:00
bbracker
38d26e857b
fix buildroot graphical sim
2021-10-31 18:33:43 -07:00
davidharrishmc
e29c577627
Added instructions for rv64i_m/D
2021-10-30 07:34:53 -07:00
David Harris
e9244e7a85
Fixed exe2memfile parsing of weird line in arch64d test
2021-10-30 07:26:18 -07:00
David Harris
f35b31f166
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-10-29 22:32:08 -07:00
David Harris
717f9d48e9
tesgen cleanup, added riscv-arch-test D tests
2021-10-29 22:31:48 -07:00
David Harris
f7acd31bcb
rearranging testgen
2021-10-29 22:28:37 -07:00
Ross Thompson
74d0fb60ab
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-10-29 12:46:23 -05:00
Ross Thompson
8aad95366d
Fixed the 4 way set associative pseudo LRU replacement policy.
2021-10-29 12:46:02 -05:00
kipmacsaigoren
8db0b5c06f
added missing destination for copy command
2021-10-29 11:46:18 -05:00
Ross Thompson
f61fcd25a9
Possible fix for the incorrect behavior of the pseudo LRU replacement policy for 4 ways set associative caches.
2021-10-29 11:03:37 -05:00
kipmacsaigoren
220c58045d
added timing through redundant multiplier to mdu timing report.
2021-10-28 22:43:58 -05:00
kipmacsaigoren
aaef7977f6
made make also save the netlist and log file to outputs
2021-10-28 22:37:25 -05:00
Ross Thompson
54c714d222
Applied batch from fpga branch which fixes the dcache fence bug. The should cause the dcache to flush all dirty cache lines to main memory. The bug caused the dirty reset to clear each way for a particular line.
2021-10-28 11:07:18 -05:00
bbracker
fe2bf13720
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-10-27 14:40:31 -07:00
