Katherine Parry
539d21645f
some fpu lint warnings fixed - still working on it
2021-10-11 18:32:03 -07:00
Shreya Sanghai
0acf9fd746
made redunantmul generate DW02_multp for synopsys sythnesis
2021-10-11 11:54:39 -07:00
Shreya Sanghai
84ff2b49c7
actually added redundant mul
2021-10-11 11:29:13 -07:00
Shreya Sanghai
a1c9ffdf2b
added redundant multiplier
2021-10-11 11:20:12 -07:00
David Harris
ab6a796690
Starting to optimize multiplier
2021-10-11 11:06:07 -07:00
David Harris
f1190b6ceb
intdiv cleanup
2021-10-11 08:14:21 -07:00
David Harris
4139f27d10
Divider FSM simplification
2021-10-10 22:24:14 -07:00
David Harris
75c17dc372
Major reorganization of regression and simulation and testbenches
2021-10-10 15:07:51 -07:00
David Harris
a6c6b2b974
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-10-10 12:26:15 -07:00
David Harris
caf3c2de9b
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-10-10 12:25:11 -07:00
bbracker
90ccd60790
simplify flopenrc's that didn't actually need to be flopenrc's
2021-10-10 12:25:05 -07:00
David Harris
43d92f2507
Divider cleanup
2021-10-10 12:24:44 -07:00
David Harris
6704e37597
Simplifying divider FSM
2021-10-10 12:21:43 -07:00
David Harris
4deae8019a
Simplifying divider FSM
2021-10-10 12:21:36 -07:00
David Harris
2759f1fcb1
Moved & ~StallM from FSM into DivStartE
2021-10-10 11:49:32 -07:00
David Harris
635fe181f8
Moved divide iteration register names to M stage
2021-10-10 11:30:53 -07:00
David Harris
b713b6ca87
Simplified remainder for divide by 0
2021-10-10 11:20:07 -07:00
David Harris
6988c8c37c
divider control signal simplificaiton
2021-10-10 10:55:02 -07:00
David Harris
c2bb0324c6
Removed negedge flops from divider
2021-10-10 10:41:13 -07:00
David Harris
3aa9e088c8
Simplified divider sign handling
2021-10-10 08:35:26 -07:00
David Harris
39bbeefa78
renamed DivStart
2021-10-10 08:32:04 -07:00
David Harris
64ed267825
renamed DivSigned
2021-10-10 08:30:19 -07:00
Katherine Parry
77fe00947e
FMA matches diagram and lint warnings fixed
2021-10-09 17:38:10 -07:00
kipmacsaigoren
96565f9435
rename adder in fpu for synthesis
2021-10-08 17:47:54 -05:00
kipmacsaigoren
7fde7aae6e
Merging new changes into the old one's I've made in the OKstate servers
2021-10-08 17:47:11 -05:00
Kip Macsai-Goren
f3058f94c6
removed loops and simplified mask generation logic. PMP's now pass my tests and linux tests up to around 300M instructions.
2021-10-08 15:33:18 -07:00
kipmacsaigoren
2d4623b49c
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-10-08 12:01:44 -05:00
bbracker
1824b2af13
fix div restarting bug
2021-10-07 18:55:00 -04:00
kipmacsaigoren
8db7ce002d
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-10-06 11:52:34 -05:00
James E. Stine
a91c0c8fc7
Make changes to fpdiv - still working on clock issue with fsm that was changed from posedge to negedge - also updated fpdivsqrt rounding to handle testfloat
2021-10-06 08:26:09 -05:00
kipmacsaigoren
b72e94badf
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-10-04 12:28:03 -05:00
David Harris
36bbf0c502
Divider cleaup
2021-10-03 11:22:34 -04:00
David Harris
10ef563211
Divider cleanup
2021-10-03 11:16:48 -04:00
David Harris
78eba19a1f
Replacing XE and DE with SrcAE and SrcBE in divider
2021-10-03 11:11:53 -04:00
David Harris
48e33c79a9
Reduced cycle count for DIVW/DIVUW by two
2021-10-03 09:42:22 -04:00
David Harris
648cc8ef64
Divider comments cleanup
2021-10-03 01:12:40 -04:00
David Harris
2ae51d1852
Parameterized number of bits per cycle for integer division
2021-10-03 01:10:15 -04:00
David Harris
81601e26a3
Divider cleanup
2021-10-03 00:41:41 -04:00
David Harris
c690a863b5
Added suffixes to more divider signals
2021-10-03 00:32:58 -04:00
David Harris
0c08a7c05c
More divider cleanup
2021-10-03 00:20:35 -04:00
David Harris
5e6b2490cb
Eliminated extra inversion for subtraction in divider
2021-10-03 00:10:12 -04:00
David Harris
418e9cd6e6
Added more pipeline stage suffixes to divider
2021-10-03 00:06:57 -04:00
David Harris
b3bded9e6c
Added more pipeline stage suffixes to divider
2021-10-02 22:54:01 -04:00
David Harris
5db800fac3
Divider mostly cleaned up
2021-10-02 21:10:35 -04:00
David Harris
3a85c972b6
Partial divider cleanup 3
2021-10-02 21:00:13 -04:00
David Harris
5d64f04752
Partial divider cleanup 2
2021-10-02 20:57:54 -04:00
David Harris
f913305993
Partial divider cleanup
2021-10-02 20:55:37 -04:00
David Harris
afd6babc13
Divider code cleanup
2021-10-02 10:41:09 -04:00
David Harris
e33ef58e67
Added negative edge triggered flop to save inputs; do absolute value in first cycle for signed division
2021-10-02 10:36:51 -04:00
David Harris
4926ae343a
Divider code cleanup
2021-10-02 10:13:49 -04:00
David Harris
852eb24731
Moved negating divider otuput to M stage
2021-10-02 10:03:02 -04:00
David Harris
9d63aa683f
Moved muldiv result selection to M stage for performance
2021-10-02 09:38:02 -04:00
David Harris
fbe6e41169
Divide performs 2 steps per cycle
2021-10-02 09:19:25 -04:00
David Harris
e11c565a6f
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-09-30 23:15:34 -04:00
bbracker
6aa79657ed
Revert "first attempt at verilog side of checkpoint functionality"
...
This reverts commit fec96218f6
2021-09-30 20:45:26 -04:00
David Harris
caa36f267d
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-09-30 20:07:43 -04:00
David Harris
9d8e7f2714
Integer Divide/Rem passing all regression.
2021-09-30 20:07:22 -04:00
David Harris
760f4d66dd
RV32 div/rem working signed and unsigned
2021-09-30 15:24:43 -04:00
David Harris
42d573be57
SRT Division unsigned passing Imperas tests
2021-09-30 12:17:24 -04:00
bbracker
fec96218f6
first attempt at verilog side of checkpoint functionality
2021-09-28 23:17:58 -04:00
kipmacsaigoren
523d25ee7b
Merge branch 'ppa' into main
2021-09-20 01:01:47 -05:00
Ross Thompson
221dbe92b2
Fixed the amo on dcache miss cpu stall issue.
2021-09-17 22:15:03 -05:00
Ross Thompson
e16c27225b
Finished adding the d cache flush. Required ensuring the write data, address, and size are
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correct when transmitting to AHBLite interface.
2021-09-17 13:03:04 -05:00
Kip Macsai-Goren
4de4774a71
more input changes on prioirty thermometer. passes lint
2021-09-17 13:07:21 -04:00
kipmacsaigoren
cc4ad218cb
added new fun ways of putting inputs into the priority thermometer
2021-09-17 12:00:38 -05:00
Ross Thompson
cfd522da6b
The E stage needs to be flushed on InvalidateICacheM. FlushM should be asserted.
2021-09-17 10:33:57 -05:00
Ross Thompson
0b1e59d075
Updated Dcache to fully support flush. This appears to work.
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Updated PCNextF so it points to the correct PC after icache invalidate.
Build root crashes with PCW mismatch and invalid register writes.
2021-09-17 10:25:21 -05:00
Ross Thompson
615fd41e7b
Added states and all control and data path logic to support d cache flush. This is currently untested; however the existing regresss test passes.
2021-09-16 18:32:29 -05:00
Ross Thompson
348187ea70
Added counters to walk through d cache flush.
2021-09-16 17:12:51 -05:00
Ross Thompson
d901f60a6d
Added flush controls to cachway.
2021-09-16 16:56:48 -05:00
Ross Thompson
cae350abb7
Added invalidate to icache.
2021-09-16 16:15:54 -05:00
kipmacsaigoren
97c474327c
changed priority circuits for synthesis and light cleanup
2021-09-15 12:24:24 -05:00
David Harris
9ae25b0cea
Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.
2021-09-15 13:14:00 -04:00
David Harris
9fa048980d
Fixed MTVAL contents during breakpoint. Now all riscv-arch-test vectors pass in rv32 and rv64
2021-09-13 12:40:40 -04:00
David Harris
bbb6c7bef7
Restored old integer divider
2021-09-12 22:07:52 -04:00
David Harris
dd1e7548ed
Modified rxfull determination in UART, started division
2021-09-12 20:00:24 -04:00
Ross Thompson
be864abcc5
Fixed bug with or_rows.
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If ROWS == 1 then the output was always X. Fixed by adding if to check if ROWS==1.
2021-09-11 15:51:11 -05:00
Ross Thompson
570aab4275
Fixed FPGA synthesis bug in the fpdiv fsm. Was creating latches.
2021-09-11 15:40:27 -05:00
Ross Thompson
5744796431
Fixed dcache to prevent latches in FPGA synthesized design.
2021-09-11 12:03:48 -05:00
Ross Thompson
6f4542f063
Third attempt at fixing the write enables for the icache cacheway.
2021-09-09 15:08:10 -05:00
Ross Thompson
6965bde95c
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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Refixed some bit width issues in the icache.
2021-09-09 12:44:02 -05:00
Ross Thompson
1d370ca71f
fixed some lint bugs.
2021-09-09 12:38:57 -05:00
David Harris
12bd351edf
Lint cleaning, riscv-arch-test testing
2021-09-09 11:05:12 -04:00
David Harris
9480f8efdb
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-09-08 16:00:12 -04:00
David Harris
118cb7fb87
Added testbench-arch for riscv-arch-test suite
2021-09-08 15:59:40 -04:00
Ross Thompson
6550f38af9
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-09-08 12:47:03 -05:00
bbracker
bb84354a47
fixed bug where M mode was sensitive to S mode traps
2021-09-07 19:14:39 -04:00
Ross Thompson
49e75d579c
Set associate icache working, but way 0 is never written.
2021-09-07 12:46:16 -05:00
Ross Thompson
05455f8392
Changed name of memory in icache.
2021-09-06 20:54:52 -05:00
James E. Stine
02a1fda650
Not sure I understand the Misaligned hptw - seems like a bug and should be L1_ADR instead of L0_ADR
2021-09-03 10:26:38 -05:00
Ross Thompson
2968623f9a
Partial multiway set associative icache.
2021-08-30 10:49:24 -05:00
Katherine Parry
70f332fe2f
FMA cleanup
2021-08-28 10:53:35 -04:00
Ross Thompson
6a9fa2fae3
Fixed bugs I introduced to the icache.
2021-08-27 15:00:40 -05:00
Ross Thompson
d433db3048
Renamed PCMux (icache) to SelAdr to match dcache.
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Removed unused cache files.
2021-08-27 11:14:10 -05:00
Ross Thompson
96cbd8e785
Modified icache to no longer need StallF in the PCMux logic. Instead this is handled in the icachefsm.
...
One downside is it increases the icache complexity. However it also fixes an untested bug. If a region
was uncacheable it would have been possible for the request to be made multiple times. Now that is
not possible. Additionally spills were oscillating between the spill hit states without this change.
The impact was 'benign' as the final spilled instruction always had the correct upper 16 bits.
2021-08-27 11:03:36 -05:00
Ross Thompson
4ace7fe946
Renamed ICacheCntrl to icachefsm.
2021-08-26 15:57:17 -05:00
Ross Thompson
d6ff89b7e6
Swapped out the icachemem for cacheway. cacheway is modified to optionally support dirty bits.
2021-08-26 15:43:02 -05:00
Ross Thompson
aea7afead6
Finished moving data path logic from the ICacheCntrl.sv to icache.sv.
2021-08-26 13:06:24 -05:00
Ross Thompson
86fc632790
Moved data path logic from icacheCntrl to icache.
2021-08-26 10:58:19 -05:00
Ross Thompson
fd28c4f556
Removed unused logic in icache.
2021-08-26 10:49:54 -05:00
