230 Commits

Author	SHA1	Message	Date
Jarred Allen	5f4feb0ff1	Works for misaligned instructions not on line boundaries	2021-03-25 15:42:17 -04:00
Jarred Allen	3b4f0141f4	Begin work on compressed instructions	2021-03-25 14:43:10 -04:00
Jarred Allen	0290568a52	Make cache output NOP after a reset	2021-03-25 13:18:30 -04:00
Jarred Allen	ce6f102fc5	Clean up some stuff	2021-03-25 13:04:54 -04:00
Jarred Allen	128278ea27	Working for all of rv64i now, but not compressed instructions	2021-03-25 13:02:26 -04:00
Jarred Allen	602271ff7b	rv64i linear control flow now working	2021-03-25 13:02:26 -04:00
Jarred Allen	ba95557c44	More progress on icache controller	2021-03-25 13:01:11 -04:00
Jarred Allen	ad0d77e9e1	Begin rewrite of icache module to use a direct-mapped scheme	2021-03-25 13:01:10 -04:00
Jarred Allen	ebd6b931c6	Fix bug in cache line	2021-03-25 12:59:30 -04:00
Jarred Allen	b774d35c34	Output NOP instead of BAD when reset	2021-03-25 12:42:48 -04:00
Jarred Allen	4b92a595ab	Merge branch 'main' into cache ... Conflicts: wally-pipelined/src/uncore/dtim.sv	2021-03-25 12:10:26 -04:00
Thomas Fleming	e3900bd0fa	Finish finite state machines for page table walker	2021-03-25 02:48:40 -04:00
Thomas Fleming	b5003b093a	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2021-03-25 02:35:21 -04:00
bbracker	a3788eb218	added 1 tick delay to dtim flops	2021-03-25 02:23:30 -04:00
bbracker	b5fa410e15	added 1 tick delay on tim reads	2021-03-25 02:15:28 -04:00
Jarred Allen	682050a33b	Merge branch 'main' into cache ... Conflicts: wally-pipelined/src/ifu/ifu.sv	2021-03-25 00:51:12 -04:00
bbracker	67b27cd2f5	instrfault direspecting stalls bugfix	2021-03-25 00:44:35 -04:00
bbracker	02e924e55a	instrfaults not respecting stalls bugfix	2021-03-25 00:16:26 -04:00
bbracker	1e3f683a9d	upgraded gpio bus interface	2021-03-25 00:15:02 -04:00
bbracker	e98dd420bc	future work comment about suspicious-looking verilog in csri.sv	2021-03-25 00:10:44 -04:00
Thomas Fleming	b1d849c822	Add all PMP addr registers	2021-03-24 21:58:33 -04:00
Katherine Parry	18cb1f4873	fixed various bugs in the FMA	2021-03-24 21:51:17 +00:00
Jarred Allen	c1fe16b70b	Give some cache mem inputs a better name	2021-03-24 12:31:50 -04:00
Jarred Allen	a51257abca	Fix compile errors from const not actually being constant (why does Verilog do this)	2021-03-24 00:58:56 -04:00
Jarred Allen	4410944049	Merge branch 'main' into cache	2021-03-23 23:35:36 -04:00
Katherine Parry	56dc8de009	fixed various bugs in the FMA	2021-03-24 01:35:32 +00:00
Jarred Allen	d6ecc3ede0	Begin work on direct-mapped cache	2021-03-23 17:03:02 -04:00
Teo Ene	ef3d2dda48	Added BOOTTIM to InstrAccessFaultF calculation in uncore/imem	2021-03-23 15:21:13 -05:00
Shreya Sanghai	1d6a2989ed	PC counts branch instructions	2021-03-23 14:25:51 -04:00
Jarred Allen	0f8fe8fb3b	Document some internal signals	2021-03-23 00:10:35 -04:00
Jarred Allen	6ffa01cc4d	Add comments explaining icache inputs	2021-03-23 00:07:39 -04:00
Jarred Allen	827993598d	Small commit to see if new hook tests non-main branch	2021-03-22 23:57:01 -04:00
Noah Boorstin	15474f678d	Merge branch 'main' into cache	2021-03-22 23:28:30 -04:00
bbracker	5efd5958e7	added delays to uart AHB signals	2021-03-22 15:40:29 -04:00
Jarred Allen	6ce52f9b80	Remove DelaySideD since it isn't needed	2021-03-22 15:13:23 -04:00
Jarred Allen	b871bfe714	Update icache interface	2021-03-22 15:04:46 -04:00
Jarred Allen	3748d03adc	Merge branch 'main' into cache	2021-03-22 13:47:48 -04:00
bbracker	11d4a8ab34	first pass at PLIC interface	2021-03-22 10:14:21 -04:00
Katherine Parry	f741ba7702	fixed various bugs in the FMA	2021-03-21 22:53:04 +00:00
Jarred Allen	f9cf05a7d4	Fix bug with PC incrementing	2021-03-20 18:06:03 -04:00
Jarred Allen	a3a646d1a9	Merge branch 'main' into cache	2021-03-20 17:56:25 -04:00
Jarred Allen	a2bf5ac202	Fix another bug in the icache (why so many of them?)	2021-03-20 17:54:40 -04:00
Jarred Allen	c5f99c4a34	Revert "Change flop to listen to StallF" ... This reverts commit c8028710a5.	2021-03-20 17:34:19 -04:00
Jarred Allen	c8028710a5	Change flop to listen to StallF	2021-03-20 17:04:13 -04:00
Katherine Parry	e317e7511e	messy FMA rewrite using section 7.5.4 in The Handbook of Floating-Point Arithmetic	2021-03-20 02:05:16 +00:00
Jarred Allen	279c09b27c	Merge changes from main	2021-03-18 18:58:10 -04:00
bbracker	85363e941d	AHB bugfixes and sim waveview refactoring	2021-03-18 18:25:12 -04:00
bbracker	98e93a63c0	maybe AHB works now	2021-03-18 17:47:00 -04:00
Shreya Sanghai	bbe0957df5	Merge branch 'gshare' into main ... Conflicts: wally-pipelined/regression/wave.do	2021-03-18 17:25:48 -04:00
Ross Thompson	1091dd10c1	Switched to gshare from global history. ... Fixed a few minor bugs.	2021-03-18 16:05:59 -05:00