Ross Thompson
365a6e9f7a
Added check for the odd Ubuntu 22.04 python2/3 issue.
2023-01-21 21:29:37 -06:00
Ross Thompson
f82e7474d9
More improvements to the tool install script.
2023-01-21 21:23:23 -06:00
Ross Thompson
b460b780aa
Working toolchain install script for ubuntu.
2023-01-21 20:52:58 -06:00
Ross Thompson
70005c4c48
fixes to installer script
2023-01-21 18:00:14 -06:00
Ross Thompson
59b770ad15
fixes to install script.
2023-01-21 17:32:44 -06:00
Ross Thompson
a748cc1acb
Updates to tool install script
2023-01-21 17:24:21 -06:00
Ross Thompson
b28895b662
Created a tool chain install script for ubuntu 22.04.
2023-01-21 14:03:30 -06:00
Mike Thompson
1fed4b16cc
Merge pull request #15 from ross144/main
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Updates to FPGA synthesis flow and removal of debug markers
2023-01-21 10:31:21 -05:00
Ross Thompson
64eaaa670c
More fixes for the debug2.xdc constraints.
2023-01-20 20:48:19 -06:00
Ross Thompson
6f0b184677
Merge remote-tracking branch 'upstream/main'
2023-01-20 20:30:44 -06:00
Ross Thompson
ee4c78c7fa
More fixes to fpga ila debugger.
2023-01-20 20:28:21 -06:00
Ross Thompson
3effeb42c3
Fixed fpga constraints.
2023-01-20 20:18:04 -06:00
Ross Thompson
442de3f5b7
Updated fpga constraints.
2023-01-20 20:16:33 -06:00
Ross Thompson
a4822c9f54
Added license and comments to new script.
2023-01-20 19:50:33 -06:00
Ross Thompson
b709c224ab
Updated ignore to exclude copied files.
2023-01-20 19:47:33 -06:00
Ross Thompson
e06237ad92
Removed mark_debug vivado directive from source code.
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Created script to add mark_debug directive to source code based on a file which contains locations and signal which need them for the FPGA debugger.
Files output to temporary directory.
2023-01-20 19:43:18 -06:00
Ross Thompson
626bcd8608
Removed mark_debug from all source code.
2023-01-20 18:47:36 -06:00
davidharrishmc
06661d1d16
Merge pull request #14 from ross144/main
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Test commit.
2023-01-20 15:31:25 -08:00
Ross Thompson
9d8fed1d35
Test commit.
2023-01-20 17:27:09 -06:00
David Harris
45218863af
test
2023-01-20 15:23:38 -08:00
David Harris
3d13683c07
Continued framework for B instructions
2023-01-20 14:27:13 -08:00
David Harris
a968ae2f66
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2023-01-20 14:19:10 -08:00
David Harris
e87c2b2724
Started adding bit manipulation unit
2023-01-20 14:19:07 -08:00
Ross Thompson
b25b93df11
Repaired fpga debugger.
2023-01-20 15:26:52 -06:00
Ross Thompson
0123776037
Updated figure cache references.
2023-01-20 15:01:54 -06:00
Ross Thompson
3e1a54e80a
Removed SDC from repo due to copy right issue.
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Modified fpga build flow to reference it outside the repo.
2023-01-20 14:57:06 -06:00
Ross Thompson
2e9b5f9ae4
Formatting.
2023-01-20 13:13:05 -06:00
Ross Thompson
bcadbd7104
Formatting.
2023-01-20 13:09:42 -06:00
Ross Thompson
ecceea177a
Formatting.
2023-01-20 13:05:10 -06:00
Ross Thompson
3d202ed2fd
Reformatting cachefsm.
2023-01-20 12:49:55 -06:00
Ross Thompson
d3df8e062e
Formatting.
2023-01-20 12:41:57 -06:00
Ross Thompson
1ecf4e4cc9
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
2023-01-20 12:37:12 -06:00
Ross Thompson
74ab386735
More cleanup and formatting.
2023-01-20 12:34:40 -06:00
David Harris
26cb45e240
renamed comparator module
2023-01-20 10:13:47 -08:00
David Harris
64080ac098
Updated HMC Synopysys license manager
2023-01-20 10:13:20 -08:00
Ross Thompson
340e1797ea
More cleanup and formatting.
2023-01-20 12:09:21 -06:00
Ross Thompson
c5169a3e39
Formatting.
2023-01-20 11:51:10 -06:00
Ross Thompson
5b5a615e4a
Integrated the missing zifence tests into the regression test.
2023-01-20 10:34:49 -06:00
Ross Thompson
29f45d6203
Imperas found a bug with the Fence.I instruction.
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If a fence.i directly followed a store miss, the d$ would release Stall during the cache line write.
Then transition to ReadHold. This cause the d$ flush to go high while in ReadHold. The solution is
to ensure the cache continues to assert Stall while in WriteLine state.
There was a second issue also. The D$ flush asserted FlushD which flushed the I$ invalidate.
Finally the third issue was CacheEn from the FSM needs to be asserted on an InvalidateCache.
2023-01-20 10:17:21 -06:00
Ross Thompson
2cca457f14
Imperas found a bug with the Fence.I instruction.
...
If a fence.i directly followed a store miss, the d$ would release Stall during the cache line write.
Then transition to ReadHold. This cause the d$ flush to go high while in ReadHold. The solution is
to ensure the cache continues to assert Stall while in WriteLine state.
There was a second issue also. The D$ flush asserted FlushD which flushed the I$ invalidate.
Finally the third issue was CacheEn from the FSM needs to be asserted on an InvalidateCache.
2023-01-20 09:41:18 -06:00
Ross Thompson
ce7d92f2dc
Merge branch 'imperas' of github.com:davidharrishmc/riscv-wally into imperas
2023-01-20 08:38:08 -06:00
Lee Moore
5de1801100
Merge pull request #13 from eroom1966/imperas
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Merge pull request #5 from davidharrishmc/imperas
2023-01-20 14:34:38 +00:00
Lee Moore
bc0497687c
Merge pull request #5 from davidharrishmc/imperas
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Merge pull request #12 from eroom1966/imperas
2023-01-20 14:33:21 +00:00
Lee Moore
97619eee87
Merge pull request #12 from eroom1966/imperas
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Imperas
2023-01-20 14:32:57 +00:00
Lee Moore
9dd771933b
Merge pull request #4 from davidharrishmc/imperas
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Merge pull request #11 from eroom1966/imperas
2023-01-20 14:32:21 +00:00
eroom1966
9fe515c78e
Merge branch 'imperas' of https://github.com/eroom1966/riscv-wally into imperas
2023-01-20 14:31:17 +00:00
Ross Thompson
da4eec7e0e
Improved comment.
2023-01-19 17:41:57 -06:00
Ross Thompson
117ff8163b
ram uses always rather than always_ff due to modelsim issue.
2023-01-19 17:41:15 -06:00
Ross Thompson
23ab178192
Merge branch 'main' of github.com:davidharrishmc/riscv-wally
2023-01-19 17:28:53 -06:00
Ross Thompson
928e06d4fa
Added comment about needed changes in BTB.
2023-01-19 17:28:00 -06:00
