David Harris
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48e33c79a9
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Reduced cycle count for DIVW/DIVUW by two
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2021-10-03 09:42:22 -04:00 |
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David Harris
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2ae51d1852
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Parameterized number of bits per cycle for integer division
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2021-10-03 01:10:15 -04:00 |
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David Harris
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9ae25b0cea
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Added Zfencei support in instruction decoder and configurations. Also added riscv-arch-test 32-bit tests to regression.
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2021-09-15 13:14:00 -04:00 |
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Ross Thompson
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570aab4275
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Fixed FPGA synthesis bug in the fpdiv fsm. Was creating latches.
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2021-09-11 15:40:27 -05:00 |
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Ross Thompson
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86fbe2a654
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Changed configs to support 4 ways set associative caches.
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2021-09-08 12:52:49 -05:00 |
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Ross Thompson
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6550f38af9
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-09-08 12:47:03 -05:00 |
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Ross Thompson
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49e75d579c
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Set associate icache working, but way 0 is never written.
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2021-09-07 12:46:16 -05:00 |
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Katherine Parry
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70f332fe2f
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FMA cleanup
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2021-08-28 10:53:35 -04:00 |
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Katherine Parry
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aedd71d570
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move some FPU select muxs to execute stage
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2021-08-13 14:41:22 -04:00 |
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Katherine Parry
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e00f181bcf
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LZA added to FMA and attemting a merged FMA and adder in synthesis
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2021-08-10 13:57:16 -04:00 |
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Ross Thompson
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c749d08542
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fixed the read timer issue but we still have problems with interrupts and i/o devices.
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2021-08-06 10:16:06 -05:00 |
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Katherine Parry
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ef28679721
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fpu cleanup
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2021-07-24 14:59:57 -04:00 |
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bbracker
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d3059dd04c
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fix UART RX FIFO bug where tail pointer can overtake head pointer
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2021-07-22 02:09:41 -04:00 |
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Katherine Parry
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b9081e514c
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FMA parameterized
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2021-07-20 22:04:21 -04:00 |
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David Harris
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1f3dfa20f6
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flag for optional boottim
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2021-07-20 14:46:37 -04:00 |
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David Harris
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e1a1a8395e
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Parameterized I$/D$ configurations and added sanity check assertions in testbench
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2021-07-20 08:57:13 -04:00 |
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Ross Thompson
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508c3e35af
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Restored TIM range.
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2021-07-19 21:17:31 -05:00 |
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David Harris
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4d40b5faef
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Added cache configuration to config files
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2021-07-19 18:19:46 -04:00 |
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David Harris
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46ab609498
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Updated FMA1 with parameterized size
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2021-07-18 20:40:49 -04:00 |
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David Harris
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4f8f52f283
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Added FLEN, NE, NF to config and started using these in FMA1
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2021-07-18 17:28:25 -04:00 |
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David Harris
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8d348dacce
|
Started atomics
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2021-07-17 21:11:41 -04:00 |
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David Harris
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1bd5c137a6
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Reduced size of physical memory by 16 for performance
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2021-07-16 20:10:12 -04:00 |
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Ross Thompson
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6521d2b468
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Also changed the shadow ram's dcache copy widths.
Merge branch 'dcache' into main
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2021-07-16 14:21:09 -05:00 |
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Ross Thompson
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1aabee0478
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Updated the config so the tim has a bigger range.
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2021-07-16 12:35:00 -05:00 |
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Katherine Parry
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c74d26eea4
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Fixed lint warning
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2021-07-14 21:24:48 -04:00 |
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Katherine Parry
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efdec72df1
|
Fixed writting MStatus FS bits
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2021-07-13 13:20:30 -04:00 |
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Katherine Parry
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36f59f3c99
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Almost all convert instructions pass Imperas tests
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2021-07-11 18:06:33 -04:00 |
|
Abe
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84711fbdc8
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Updated MISA defining as well as porting sizes for peripherals (34 to 56)
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2021-07-07 02:37:09 -04:00 |
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David Harris
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71711c54c9
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Don't generate HPTW when MEM_VIRTMEM=0
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2021-07-05 23:35:44 -04:00 |
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David Harris
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6bac566bb7
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Added support for TVM flag in CSRS and to disabl TLB when MEM_VIRTMEM = 0
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2021-07-05 20:35:31 -04:00 |
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David Harris
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80666f0a71
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Added ASID & Global PTE handling to TLB CAM
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2021-07-04 17:52:00 -04:00 |
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David Harris
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ccd9c05303
|
Switched to array notation for pmpchecker
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2021-07-04 10:51:56 -04:00 |
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David Harris
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9645b023c9
|
Moved BOOTTIM to 0x1000-0x1FFF. Added logic to detect an access to undefined memory and assert HREADY so bus doesn't hang.
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2021-07-04 01:19:38 -04:00 |
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Ross Thompson
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7b3716c281
|
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2021-07-02 13:56:49 -05:00 |
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Ross Thompson
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dbd33465e1
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Merge branch 'main' into bigbadbranch
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2021-07-02 11:52:26 -05:00 |
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David Harris
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76a43eb468
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Optimized PMP checker logic and added support for configurable number of PMP registers
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2021-07-02 11:05:25 -04:00 |
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Ross Thompson
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d6c19e73f4
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Regression test runs further. The LSU state machine which fakes the Dcache had a few bugs. MemAccessM needed to be squashed on bus faults.
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2021-06-25 11:05:17 -05:00 |
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Kip Macsai-Goren
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d7e518991e
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Light cleanup of signals, style. Changed several signals to account for new Phys Addr sizes as opposed to HADDR.
|
2021-06-24 20:01:11 -04:00 |
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Ross Thompson
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aeeaf6d919
|
Progress.
|
2021-06-24 13:05:22 -05:00 |
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David Harris
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d2ec04564b
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Cleaned up fcsr code and added _SUPPORTED to optionally disable peripherals
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2021-06-20 22:59:04 -04:00 |
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bbracker
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23f479d225
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remove OVP_CSR_CONFIG because it is an alias of BUSYBEAR
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2021-06-20 22:38:25 -04:00 |
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Katherine Parry
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2b67f25683
|
all rv64f instructions except convert, divide, square root, and FLD pass
|
2021-06-20 20:24:09 -04:00 |
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bbracker
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83a0a37f8e
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make xCOUNTEREN what buildroot expects it to be
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2021-06-20 09:22:31 -04:00 |
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bbracker
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a3eafc6e5b
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change buildroot config to use relative path for testvectors
|
2021-06-18 22:28:07 -04:00 |
|
Abe
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a0a4b09c94
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Updated directory coremark_bare's wally-config file to define PMP_ENTRIES
|
2021-06-18 11:46:25 -04:00 |
|
David Harris
|
35c74348a4
|
allow all size memory access in CLINT; added underscore to peripheral address symbols
|
2021-06-18 08:05:50 -04:00 |
|
David Harris
|
679e507cc6
|
Added SUPPORTED to each peripheral in each config file
|
2021-06-17 21:36:32 -04:00 |
|
David Harris
|
da8eb7749f
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Started simplifying PMA checker
|
2021-06-17 16:28:06 -04:00 |
|
Katherine Parry
|
4177f4f148
|
Updated FMA
|
2021-06-14 13:42:53 -04:00 |
|
David Harris
|
49b5fa3994
|
Reverted MIDELEG and MEDELEG to XLEN so busybear passes
|
2021-06-10 23:47:32 -04:00 |
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