Commit Graph

12 Commits

Author SHA1 Message Date
Ross Thompson
5ce4ac963f Updated arty a7 fpga top. 2023-07-17 15:55:57 -05:00
Ross Thompson
c463bd8cdd Fixed the reset for Arty A7 and now partially boots. Copies flash card to dram.
but the data is wrong.
2023-04-19 10:35:18 -05:00
Ross Thompson
d783456746 Found the first issue. the axi clock converter was stuck in reset because the polarity was reversed. 2023-04-18 17:45:41 -05:00
Ross Thompson
667524efcb Added more signals to debugger in hopes I can figure out why the mig is not responding. 2023-04-18 15:51:52 -05:00
Ross Thompson
2df6c6cb0f It's almost working. 2023-04-18 14:24:59 -05:00
Ross Thompson
ac95087042 Improved constraints and set ddr3 voltage to correct 1.35V. This voltage is only for synthesis. However I'm concerned because the gui did not let me select 1.35V. 2023-04-17 20:05:59 -05:00
Ross Thompson
8bebc56b56 Finally we are building the fpga and can view the ila. we are getting out of reset, but we are stuck at PCM = 10b8. 2023-04-17 18:39:25 -05:00
Ross Thompson
8377ff8c51 Dang. Looks like the reset button on the arty a7 is actually resetn. I wish they'd named it that way. 2023-04-17 16:37:18 -05:00
Ross Thompson
96781e0b2a Yay! We now have a functional ila and the uart connection on the pc side works. However the CPU is stuck in reset. Not really sure what's going on there. 2023-04-17 16:00:02 -05:00
Ross Thompson
d2272c0620 Found and fixed the major architecture issue with the mig 7 used in the arty a7 board.
mig 7 is completely different from the ddr4 mig in that the internal pll does not general the required clocks. An external mmcm is required to general two inputs clocks and the required user clock.
2023-04-15 11:13:28 -05:00
Ross Thompson
2abd164d03 Fixed syntax errors in arty7 top level. 2023-04-10 16:08:40 -05:00
Ross Thompson
81fb076e9e Added more support for Arty A7 board. 2023-04-10 16:01:17 -05:00