82 Commits

Author	SHA1	Message	Date
David Harris	5b7cccbc4b	Cause simplification	2022-05-12 23:33:22 +00:00
David Harris	581d841653	Cause simplification	2022-05-12 23:29:35 +00:00
David Harris	2a3f545e0c	Cause simplification	2022-05-12 23:27:02 +00:00
David Harris	c2b9fc0d8e	trap/csr cleanup	2022-05-12 22:26:21 +00:00
David Harris	292d1f33da	More trap/csr simplification	2022-05-12 22:06:03 +00:00
David Harris	662fffa830	More trap/csr simplification	2022-05-12 22:04:20 +00:00
David Harris	16b86c199c	More trap/csr simplification	2022-05-12 22:00:23 +00:00
David Harris	5f358a37c6	More trap/csr simplification	2022-05-12 21:55:50 +00:00
David Harris	21ac969c7d	Simplifying trap/csr interface	2022-05-12 21:50:15 +00:00
David Harris	072c464dc1	Simplified MTVAL logic	2022-05-12 21:36:13 +00:00
David Harris	14f9f41d2d	Partitioned privileged pipeline registers into module	2022-05-12 20:45:45 +00:00
David Harris	78448c7053	privileged cleanup	2022-05-12 20:21:33 +00:00
David Harris	dd61afb7dc	Formatting cleanup	2022-05-12 18:37:47 +00:00
David Harris	fde8375fbd	Moved Breakpoint and Ecall fault logic into privdec	2022-05-12 16:45:53 +00:00
David Harris	2ceed15bd5	Moved TLB Flush logic into privdec	2022-05-12 16:41:52 +00:00
David Harris	1e5d94bbab	Moved WFI timeout into privdec	2022-05-12 16:22:39 +00:00
David Harris	39ceb3a550	Partitioned privilege mode fsm into new module	2022-05-12 16:16:42 +00:00
David Harris	5670f77de2	More unused signal cleanup	2022-05-12 15:21:09 +00:00
David Harris	4edf9b6355	More unused signal cleanup	2022-05-12 15:15:30 +00:00
David Harris	1aa3e65bae	Removed more unused signals, simplified csri state	2022-05-12 15:10:10 +00:00
David Harris	e2e63ca9a8	Clean up unused signals	2022-05-12 14:49:58 +00:00
David Harris	545d46acb9	Simplifed mstatus.TSR handling	2022-05-12 14:09:52 +00:00
David Harris	1e7401daa0	Fixed typo in csrm	2022-05-12 06:55:39 -07:00
David Harris	9999f69922	Added MCONFIGPTR CSR hardwired to 0	2022-05-12 04:31:45 +00:00
David Harris	8166fd772e	Added M prefix for MTimerInt and MSwInt to distinguish from future supervisor SwInt	2022-05-11 15:08:33 +00:00
David Harris	137b411bea	Removed M suffix from interrupts because they are generated asynchronously to pipeline	2022-05-11 14:41:55 +00:00
David Harris	4f1b0fdc64	Preliminary support for big endian modes. Regression passes but no big endian tests written yet.	2022-05-08 06:46:35 +00:00
David Harris	1a5bfcf078	Fixed bug in delegated interrupts not being taken	2022-05-08 04:50:27 +00:00
David Harris	a516f89f22	WFI terminates when an interrupt is pending even if interrupts are globally disabled	2022-05-08 04:30:46 +00:00
David Harris	7f42ff06d2	SFENCE.VMA should be illegal in user mode	2022-05-05 15:15:02 +00:00
David Harris	f436e93fc5	SFENCE.VMA should be illegal in user mode	2022-05-05 14:59:52 +00:00
David Harris	9b7aab122e	wally32priv and wally64priv now passing WALLY-status-tw. Fixed privileged.sv to produce the correct EPC on timeouts	2022-05-05 14:37:21 +00:00
David Harris	1a7599ce94	Changed WFI to stall pipeline in memory stage	2022-05-05 02:03:44 +00:00
David Harris	4b91fddc0a	Illegal instruction fault when running FPU instruction with STATUS_FS = 0	2022-05-03 18:32:01 +00:00
David Harris	1166c40059	FPU generates illegal instruction if MSTATUS.FS = 00	2022-05-03 11:56:31 +00:00
Kip Macsai-Goren	33875b20b5	fixed initial value, timing on fs bits changing after floating point instruction	2022-04-25 19:17:29 +00:00
David Harris	0957b7040d	Restored MPRV behavior per spec	2022-04-25 14:52:18 +00:00
David Harris	1a8369b02b	Added dummy mstatus byte endianness fields tied to 0, mstatush register, removed UIE and UPIE depricated fields	2022-04-25 14:49:00 +00:00
David Harris	142636173e	Added MTINST hardwired to 0, and added timeout of U-mode WFI	2022-04-24 20:00:02 +00:00
David Harris	28e8aa4f97	Fixed InstrMisalignedFaultM mtval	2022-04-24 17:31:30 +00:00
David Harris	ffecdda6e6	Improved priority order and mtval of traps to match spec	2022-04-24 17:24:45 +00:00
Kip Macsai-Goren	bd87af478a	Changed mtval for instruction misaligned fault to get address from ieuAdrM (Jal/branch target address)	2022-04-22 22:46:11 +00:00
Ross Thompson	a5d4e39e7d	Added back the instret counter to ILA.	2022-04-17 18:44:07 -05:00
David Harris	5bb521635e	Experiments with prefix comparator; minor fixes in WFI and testbench warnings	2022-04-17 21:43:12 +00:00
David Harris	b4902a6ff9	First implementation of WFI timeout wait	2022-04-17 17:20:35 +00:00
Ross Thompson	f8bdb6db49	Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main	2022-04-16 14:59:03 -05:00
Ross Thompson	bfc68bef69	Fixed possible bugs in LRSC.	2022-04-16 14:45:31 -05:00
David Harris	6e16922aae	WFI should set EPC to PC+4	2022-04-14 17:05:22 +00:00
Ross Thompson	de868ef3a2	Possible fix for trap concurent with xret. Fixes the priority so trap has higher priority than either sret or mret. Previous code had priority to xret in the trap logic and privilege logic, but not the csrsr logic. This caused partial execution of the instruction.	2022-04-07 16:56:28 -05:00
David Harris	fb95767da0	Fixed bug with CSRRS/CSRRC for MIP/SIP	2022-04-03 20:18:25 +00:00