Jacob Pease
5a832ed828
Set default baud rate of serial output to 115200 for the VCU108.
2023-08-25 17:44:06 -05:00
Ross Thompson
b5bcb5437f
Merge branch 'main' of github.com:ross144/cvw
2023-08-02 16:51:42 -05:00
Ross Thompson
087d418c35
Updateds to vcu118 constraints and device tree.
2023-08-02 16:51:32 -05:00
Ross Thompson
eb5fb07f54
Merge branch 'main' of https://github.com/openhwgroup/cvw
2023-08-01 11:04:26 -05:00
Ross Thompson
1b237a14a1
Pushed performance of arty a7 to 23Mhz.
2023-07-31 14:13:09 -05:00
Jacob Pease
d3476b64cd
Updated VCU108 device tree for 256MB memory.
2023-07-27 17:44:31 -05:00
Ross Thompson
8dc7870e62
Updated Arty A7 fpga config and device tree to 256MiB main memory.
2023-07-25 15:11:47 -05:00
Ross Thompson
d418e4fa5e
Updated arty a7 device clock speed for 20Mhz.
2023-07-24 11:50:00 -05:00
Ross Thompson
fd187e9ee6
Merge branch 'main' of github.com:ross144/cvw
2023-07-24 10:47:05 -05:00
Ross Thompson
d239b0649e
Improved timing constraints for arty a7 to push clock speed to 20Mhz.
2023-07-24 10:46:49 -05:00
Ross Thompson
608400ac6a
Updated arty a7 device tree.
2023-07-21 19:08:45 -05:00
Ross Thompson
3eeecd2f27
Merge branch 'boot' into mergeBoot
...
Merges Jacob's new sdc controller into wally.
2023-07-21 17:43:45 -05:00
Ross Thompson
37078f3d9b
Modified the LSU/IFU and caches to improve critical path. Arty A7 went from 15 to 17Mhz. I believe we can push all the way to 20+Mhz with relatively little effort. Along the way I'm fixing up the scripts build the linux images for the flash card.
2023-07-21 13:06:27 -05:00
Ross Thompson
a5f75d568b
Added artya7 device tree.
2023-07-17 16:01:02 -05:00
Jacob Pease
142ec857ed
Modified bootloader to access GUID partitions. SDC interrupt to PLIC.
...
Since writing an SD card image generation script, the bootloader
needed to be altered to access individual binaries from specific
partitions. A new file, gpt.c with it's header gpt.h, have been added
to the bootloader to facilitate this.
The SDC has been added to the device tree for the VCU108
board. Additionally the SDC interrupt signal was added to the PLIC
node in the device tree. The PLIC itself was modified to accept the
SDC interrupt signal.
2023-07-14 13:36:44 -05:00
Ross Thompson
3de5144ae4
Updated vcu118 constraints to run cpu at 38.43Mhz.
2022-11-15 10:19:38 -06:00
Ross Thompson
b812549f38
Bumped DDR4 clock speed up from 832Mhz (1666 MT/s) to 1200 Mhz (2400 MT/s).
...
Increased CPU clock speed from 30 Mhz to 35 Mhz.
2022-11-11 15:33:03 -06:00
Ross Thompson
2e60edaedd
Added new device trees for vcu118 and vcu108 boards.
2022-10-24 17:45:10 -05:00
Ross Thompson
d68bdfbade
Updated the device tree to use 30Mhz instead of 10Mhz for the cpu timebase.
2022-10-20 15:05:39 -05:00
bbracker
8d5c231a13
change devicetree to expect only 128MB of RAM
2022-03-27 15:11:36 -07:00
bbracker
fd4556393b
rename dump-dts debug script
2022-02-10 00:10:09 +00:00
bbracker
7b52ff9fcf
continue to rename devicetree to wally-virt
2022-02-10 00:08:28 +00:00
bbracker
3ebf6d7418
rename devicetree to wally-virt
2022-02-10 00:07:29 +00:00
bbracker
f94e5560ac
add trimmed-down virt devicetree to repo for QEMU
2022-02-08 11:11:44 +00:00
