Ross Thompson
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60e6c1ffa7
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Moved cacheable signal into cache.
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2022-03-08 16:34:02 -06:00 |
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bbracker
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e3303331ef
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change genTrace to dump UART output to file so we can see how far parsing got
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2022-03-08 09:52:17 -08:00 |
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bbracker
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51e68819c4
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fix up PLIC and UART checkpointing
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2022-03-07 23:48:47 -08:00 |
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bbracker
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9dbcdca433
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change UART state saving to temporarily modify LCR so that DLAB=0 when reading addresses 0 and 1 so that we get RBR and IER instead of divisor latch registers
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2022-03-07 22:12:08 -08:00 |
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bbracker
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c2ac18b5de
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change testbench-linux.sv to use new shared location of disassembly files
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2022-03-07 20:04:08 -08:00 |
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bbracker
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52bfd65fd3
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change checkpoint generation to integrate GDB scripting more cleanly and save UART and PLIC state
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2022-03-07 17:59:49 -08:00 |
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bbracker
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a93f36824d
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modify debug.sh to not rely on external GDB script
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2022-03-07 11:56:04 -08:00 |
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bbracker
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74ff583f9b
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add debug.sh
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2022-03-07 19:52:19 +00:00 |
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Shreya Sanghai
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b73f81548f
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removed reminant changes
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2022-03-07 17:36:05 +00:00 |
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Shreya Sanghai
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b6b4d0f982
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undid changes to synth script
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2022-03-07 17:32:08 +00:00 |
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Shreya Sanghai
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31f17d2bf3
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modified synth script to take config from outputdir
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2022-03-07 17:12:43 +00:00 |
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Shreya Sanghai
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4d8e0ecf29
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updated makefile to speed up synth
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2022-03-07 00:09:18 +00:00 |
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Shreya Sanghai
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e4145d32ab
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modified makefile
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2022-03-07 00:09:18 +00:00 |
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bbracker
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01eeab2131
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update checkpointSweep in accordance to having removed trace parsing feature
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2022-03-06 14:55:51 -08:00 |
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bbracker
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c432e2175e
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remove vestigial silencePipe mechanism
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2022-03-06 14:54:35 -08:00 |
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bbracker
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ca6bb7c2d2
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needed to initialize checkpoint directory
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2022-03-06 14:51:25 -08:00 |
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bbracker
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6b1b471ca6
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no longer use cythonization on python parser scripts because its a little complicated and has marginal benefit
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2022-03-06 14:40:26 -08:00 |
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bbracker
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2e6fa01b9b
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give genCheckpoint the same de-sudo'ing treatement
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2022-03-06 14:37:12 -08:00 |
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bbracker
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675e112950
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better to use $tvDir variable rather than abs path
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2022-03-06 14:33:53 -08:00 |
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bbracker
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8720604bfc
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replace sudo's with suggestions in genRecording.sh
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2022-03-06 14:31:55 -08:00 |
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bbracker
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3e4ce15ea4
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replace sudo's in genTrace.sh with suggested commands
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2022-03-06 14:24:50 -08:00 |
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bbracker
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3e1f4decf1
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small bugfix to suggested sudo commands for linux testvectors
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2022-03-06 14:16:23 -08:00 |
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bbracker
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228f693f13
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remove checkpoint trace generation since that requires qemu hacking and because we are able to generate the whole trace on VLSI
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2022-03-06 14:04:30 -08:00 |
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bbracker
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12dd1fb8e3
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add path to Modelsim on vlsi
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2022-03-06 13:55:19 -08:00 |
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bbracker
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f86e76a4b1
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recommend sudo commands without automatically executing them in genInitMem.sh
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2022-03-06 13:30:19 -08:00 |
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bbracker
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a0d0742227
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change from clang to gcc when compiling testvector-generation executables
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2022-03-06 13:18:53 -08:00 |
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bbracker
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e2d2dbad10
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generate $WALLY in a way that works for bash and zsh
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2022-03-06 13:12:20 -08:00 |
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bbracker
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3601cc54ab
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Revert "fix "dirname: missing operand" bug from setup.sh"
This reverts commit 34c460b451.
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2022-03-06 12:48:53 -08:00 |
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David Harris
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aebb677f7a
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Restored setup.sh to use . Working for David. Not sure what is happening for Ben - are you on Bash?
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2022-03-06 13:39:53 +00:00 |
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David Harris
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e757ed1162
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Fixed merge of fpcalc
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2022-03-06 13:32:13 +00:00 |
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David Harris
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d2282d5e87
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Checked in fma16_template.v
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2022-03-06 13:29:35 +00:00 |
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bbracker
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94124cb108
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add extractFunctionRadix step to buildroot Makefile
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2022-03-05 19:02:07 -08:00 |
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bbracker
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9f7a434b20
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change genInitMem.sh to check for sufficient directory privileges rather than invoke sudo
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2022-03-05 18:04:00 -08:00 |
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bbracker
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ddae5f6518
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remove linux-testgen dir because it is now completely obsolete
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2022-03-05 17:26:30 -08:00 |
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bbracker
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34c460b451
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fix "dirname: missing operand" bug from setup.sh
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2022-03-05 17:21:34 -08:00 |
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David Harris
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41e111a44f
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Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
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2022-03-04 07:21:22 -08:00 |
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David Harris
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dab04b46fe
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Cleaned up printing and warnings in fpcalc.c
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2022-03-04 07:21:18 -08:00 |
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David Harris
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d24178aa34
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Prettied up softfloat_demo
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2022-03-04 05:16:20 +00:00 |
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David Harris
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f2bda069da
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Adjusted scripts to use
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2022-03-04 05:09:02 +00:00 |
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David Harris
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1d3cd85d59
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Defined WALLY in setup as pointer to repository
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2022-03-03 21:00:07 -08:00 |
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David Harris
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9fd861a9ee
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removed more old 64priv tests
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2022-03-04 03:57:19 +00:00 |
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bbracker
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51f1a411dd
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-03-04 00:12:00 +00:00 |
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bbracker
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1c5697874f
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comment out nonfunctioning CSR-PERMISSIONS-M test
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2022-03-04 00:11:55 +00:00 |
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David Harris
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63e9d846e4
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-03-04 00:07:34 +00:00 |
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David Harris
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48705457d5
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LSU/Cache code review notes
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2022-03-04 00:07:31 +00:00 |
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bbracker
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efb5d1dbc0
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Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-03-04 00:06:27 +00:00 |
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bbracker
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443dd40ea8
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remove imperas32p tests
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2022-03-04 00:06:18 +00:00 |
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David Harris
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5e2587df09
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Updated Makefile to reflect new Linux and Imperas situation. Updated setup to include Synopsys license file.
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2022-03-03 11:28:22 -08:00 |
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David Harris
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545f569f78
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Fixed fma files to stop breaking synthesis. Changed Makefiles to skip Imperas
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2022-03-03 15:38:08 +00:00 |
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David Harris
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080fef6436
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erge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
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2022-03-02 23:47:16 +00:00 |
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