Ross Thompson
5642918ead
Merge branch 'main' into fpga
2021-11-29 10:06:53 -06:00
Ross Thompson
d5cf6da6eb
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-11-22 11:30:14 -06:00
bbracker
cffb72042a
activate STVAL for buildroot
2021-11-21 10:40:28 -08:00
Ross Thompson
e955b17500
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-11-20 22:44:45 -06:00
Ross Thompson
055a5bd202
Removed unneeded check for icache ways.
2021-11-20 22:44:37 -06:00
Ross Thompson
9d3261ed49
Reversed bit order in uart.
2021-11-20 22:43:05 -06:00
Ross Thompson
88b4e0946f
Merge branch 'main' of github.com:davidharrishmc/riscv-wally into main
2021-11-20 22:37:15 -06:00
Ross Thompson
705572f0ac
Fixed a very complex interaction between interrupts, the icache, dcache, and hptw.
...
If an interrupt occurred at the start of an ITLB miss or DTLB miss the page table
walk should be aborted before starting.
2021-11-20 22:35:47 -06:00
bbracker
4e96d0f1db
add checkpoints to regression
2021-11-20 19:42:53 -08:00
bbracker
e5d3416258
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-11-19 20:25:06 -08:00
bbracker
713aa7faac
automatic bug finder script
2021-11-19 20:25:00 -08:00
bbracker
c07caf4fe8
increase buildroot progress expecttions; increase timeout to 20 hours
2021-11-19 12:52:11 -08:00
David Harris
82cfebfb83
Coremark Cleanup, trying compile from addins
2021-11-19 06:09:04 -08:00
David Harris
a801e0dbec
Moved exe2memfile.pl
2021-11-18 20:32:13 -08:00
David Harris
690410721d
Cleaning up CoreMark benchmark
2021-11-18 20:12:52 -08:00
David Harris
8e8b84f532
vert "Simplifying riscv-coremark"
...
This reverts commit ce8232e396
2021-11-18 18:40:13 -08:00
David Harris
ce8232e396
Simplifying riscv-coremark
2021-11-18 17:15:40 -08:00
David Harris
b73e6354e3
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-11-18 16:14:42 -08:00
David Harris
402b473dbb
CoreMark testing
2021-11-18 16:14:25 -08:00
slmnemo
0bf1836a3a
Removed .* from hazard hzu(.*).
2021-11-17 14:21:23 -08:00
slmnemo
5c28553ca1
Removed .* from hazard hzu(.*) in wallypipelinedhart.sv.
2021-11-17 14:08:08 -08:00
slmnemo
df6c54a664
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-11-17 13:38:51 -08:00
slmnemo
bf8cef78bc
removed .* from muldiv.sv (REAL)
2021-11-17 13:37:50 -08:00
David Harris
0a281a06e0
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-11-17 13:28:33 -08:00
Noah Limpert
b63c0f35d1
ieu variable naming changed for clarity
2021-11-17 13:24:28 -08:00
slmnemo
c5c886ddc1
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-11-17 13:23:20 -08:00
slmnemo
40efffc70b
Removed .*s from muldiv.sv
2021-11-17 13:23:12 -08:00
Noah Limpert
bbd17e730b
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-11-17 13:04:33 -08:00
Noah Limpert
70a84b56c8
Updated IFU variable naming for clarity
2021-11-17 12:39:05 -08:00
Kevin Kim
6437c04074
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-11-17 12:18:25 -08:00
Kevin Kim
38437c664e
root level makefile added
2021-11-17 12:17:56 -08:00
Kip Macsai-Goren
7a8c21e71f
renamed presrc to forwardedSrc, replaced SrcAE and SrcBE with Forwarded src in the muldiv
2021-11-17 10:53:17 -08:00
Ross Thompson
f4c221f20a
Created separate memory interface for the ddr4 fpga memory from the soc internal memory dtim.
2021-11-17 12:47:19 -06:00
Ross Thompson
23e78c4842
Fixed uart by reversing the bit order on transmit.
...
Set prescale to 0.
2021-11-17 10:32:41 -06:00
Skylar Litz
6fde97b16c
fixed interrupt timing bug
2021-11-16 16:46:17 -08:00
David Harris
c610be25a7
Merge branch 'main' of https://github.com/davidharrishmc/riscv-wally into main
2021-11-16 12:30:55 -08:00
bbracker
2203590f9f
get current privilege level from GDB for checkpoints
2021-11-15 14:49:00 -08:00
Ross Thompson
1c9670d739
Have linux booting. Not sure about uart, but uart is now part of the ILA and I can see TX changing.
2021-11-12 17:37:07 -06:00
Ross Thompson
7497422667
Changed several things.
...
Removed the need to use async flip flops in SDC.
Added arrs, a synchronizer for reset.
I think this works with the real FPGA hardware.
The last build did not include this arrs but it worked.
2021-11-12 11:13:50 -06:00
Skylar Litz
3dd83b3113
fix timing of delayed interrupt
2021-11-11 09:35:51 -08:00
David Harris
570f24a9e4
bringing Coremark back to life
2021-11-10 12:43:31 -08:00
Kevin Kim
7cb8b76ef6
Makefile added in regression directory:
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-cd's into imperas then runs make commands, finally running the tvLinker script
2021-11-09 10:55:48 -08:00
bbracker
f6a555009b
increase expectations for buildroot and timeout count
2021-11-06 14:57:29 -07:00
bbracker
c92d41a597
checkpoint MIDELEG support
2021-11-06 03:44:23 -07:00
bbracker
bc6332a780
fix merge conflict
2021-11-05 23:42:15 -07:00
bbracker
17e776f853
checkpoints now use binary ram files
2021-11-05 22:37:05 -07:00
Kevin
11efaa2669
changed code aligner to run recursively on a root directory
...
-only runs the aligner on .sv files
-runs recursively on sub-directories
2021-11-03 10:49:34 -07:00
bbracker
0c7681b942
fix testbench interrupt timing
2021-11-02 21:19:12 -07:00
bbracker
526aff54a8
linux testgen refactor
2021-11-01 14:09:49 -07:00
David Harris
d7f0abca5a
Add3d wally32i test
2021-11-01 13:17:49 -07:00
